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Discussion Groups | FPGA-CPU | Question reg. using BUFGCE in Virtex-II

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

Question reg. using BUFGCE in Virtex-II - Vikram Chandrasekhar - Aug 7 16:07:00 2002



Hi ,

I have a question regarding using the BUFGCE module in the Xilinx Virtex
II FPGA for disabling the global clock buffer for turning off idle
functional units.

With the "gated clock" [gated is a misnomer, it is the output of the
BUFGCE block], I am trying to register input data with a D-register. The
idea is that I can save power by turning the clock ON/OFF during idle
periods. I am experiencing weird behavior during timing simulations [The
register passes the input data one cycle late!!] and I suspect that it is
due to the "gated clock".

Any pointers as to why this behavior occurs?

Any ideas on how to intelligently disable global clock buffers in FPGA's
to reduce idle power dissipation in functional units.

Thanks in advance
Regards
Vikram

ps Sometime ago, Mr. Ricky Nite had given a location constraint for the
global clock buffers. Has this anything to do with the problem that I've
mentioned above?

Vikram Chandrasekhar
Graduate Student
Electrical and Computer Engg.
Rice University
Ph:(713)529 9819 (R)
(713)348 2897 (O)
www.ece.rice.edu/~cvikram/index.html




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