This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
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Hi, I'm currently working with a virtex FPGA and I'm studying the advantages and disadvantages of a such arithmetic circuit. For instance: full adder x CSA somatory x a cascade of CSA's in parallel multiplier x shifters tables x square-root tables circuits Did anybody do this kind of study ? or does anybody know some papers or references I can find it ? thanks, ANI --------------------------------- |
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Hi ANI. Sorry for the delay but I have been on holiday. Have a look at the following web site. http://www.iis.ee.ethz.ch/~zimmi/arith_lib.html Cheers. Robert. -----Original Message----- From: ANI . [mailto:] Sent: 14 August 2002 20:07 To: Subject: [fpga-cpu] arithmetic circuits Hi, I'm currently working with a virtex FPGA and I'm studying the advantages and disadvantages of a such arithmetic circuit. For instance: full adder x CSA somatory x a cascade of CSA's in parallel multiplier x shifters tables x square-root tables circuits Did anybody do this kind of study ? or does anybody know some papers or references I can find it ? thanks, ANI --------------------------------- To post a message, send it to: To unsubscribe, send a blank message to: |