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Discussion Groups | FPGA-CPU | How design a FIFO in Verilog?

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

How design a FIFO in Verilog? - xvibe - Aug 20 4:25:00 2002



Can you explain me how to design a FIFO in Verilog?

The FIFO that I'm talking about is of this type:

-------------------------------
| |
---| DataIN DataOUT |---
| |
---| WR# RD# |---
| |
---|> CLKIN CLKOUT <|---
| |
-------------------------------

It work's like this: The data at DataIN are shifted in at the rising edge of CLKIN adn only when WR# is low. To read the fifo, RD# must be low and the data are shifted out on the rising edge of CLKOUT. It's a typical fifo.

My problem are the two clocks.
---------------------------------





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Re: How design a FIFO in Verilog? - Author Unknown - Aug 20 7:28:00 2002


http://www.xilinx.com/xapp/xapp131.pdf
xvibe
< To:
om> cc:
Subject: [fpga-cpu] How design a FIFO in Verilog?
08/20/2002 04:25
AM
Please respond
to fpga-cpu

Can you explain me how to design a FIFO in Verilog?

The FIFO that I'm talking about is of this type:

-------------------------------
| |
---| DataIN DataOUT |---
| |
---| WR# RD# |---
| |
---|> CLKIN CLKOUT <|---
| |
-------------------------------

It work's like this: The data at DataIN are shifted in at the rising edge
of CLKIN adn only when WR# is low. To read the fifo, RD# must be low and
the data are shifted out on the rising edge of CLKOUT. It's a typical fifo.

My problem are the two clocks.
---------------------------------
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