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Discussion Groups | FPGA-CPU | Verilog to VHDL tranlator

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

C runtime library for xr16 - Jeff Chang - Sep 9 11:27:00 2002


Hi all,

Where can I find the complete c runtime library for
xr16?

Thanks,
Jeff

__________________________________________________


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RE: C runtime library for xr16 - Jan Gray - Sep 9 11:36:00 2002

> From: Jeff Chang [mailto:]
> Hi all,
>
> Where can I find the complete c runtime library for
> xr16?
>
> Thanks,
> Jeff

Alas, that does not exist.

With the XSOC Kit, or any other simple port of LCC, you get a C compiler
(and in XR16, an assembler that doubles as a simple linker). But that
is all. You have to find one of the C runtime libraries on the internet
(google.com) and adapt it to the project. Glibc expects GCC, and newlib
(if I recall correctly) requires GCC C++.

I have called GCC support "the golden key that unlocks the treasure
chest of free software", and that includes the C runtime libaries.

I personally have never taken the time to work through the GCC +
binutils code base to port it to a new ISA. In this space it has been
done several times, Nios, OpenRISC, MicroBlaze, Tensilica, etc.

Jan Gray, Gray Research LLC




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Verilog to VHDL tranlator - Avi Ben-Moshe - Sep 9 11:41:00 2002

Hi,
Can you recommend on a GOOD Verilog to VHDL translator?
Thanks,
Avi




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Re: C runtime library for xr16 - Veronica Merryfield - Sep 9 15:28:00 2002

About 10 years ago there use to be a book on implementing a C runtime
library.
I suspect such a treatise is harder to find these days - indeed a quick
check on Amazon yields little.
Google, on the other hand, managers to find a number.
Perhaps http://penguinppc.org/embedded/howto/library.html would be a good
place to start.
--
Veronica Merryfield, somewhere in Cambridgeshire, UK
"The best things in life aren't things"

----- Original Message -----
From: "Jan Gray" <>
To: <>
Sent: Monday, September 09, 2002 5:36 PM
Subject: RE: [fpga-cpu] C runtime library for xr16 > > From: Jeff Chang [mailto:]
> > Hi all,
> >
> > Where can I find the complete c runtime library for
> > xr16?
> >
> > Thanks,
> > Jeff
>
> Alas, that does not exist.
>
> With the XSOC Kit, or any other simple port of LCC, you get a C compiler
> (and in XR16, an assembler that doubles as a simple linker). But that
> is all. You have to find one of the C runtime libraries on the internet
> (google.com) and adapt it to the project. Glibc expects GCC, and newlib
> (if I recall correctly) requires GCC C++.
>
> I have called GCC support "the golden key that unlocks the treasure
> chest of free software", and that includes the C runtime libaries.
>
> I personally have never taken the time to work through the GCC +
> binutils code base to port it to a new ISA. In this space it has been
> done several times, Nios, OpenRISC, MicroBlaze, Tensilica, etc.
>
> Jan Gray, Gray Research LLC >
> To post a message, send it to:
> To unsubscribe, send a blank message to:





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Re: C runtime library for xr16 - brimdavis - Sep 9 15:57:00 2002

>
> Where can I find the complete c runtime library for
> xr16?

See the "C Libraries" section of this old post for
one possible candidate:

http://groups.yahoo.com/group/fpga-cpu/message/551

Brian




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Re: Verilog to VHDL tranlator - Tony Burch - Sep 9 18:28:00 2002

Hi Avi,

There is a Verilog to VHDL, and VHDL to Verilog
translator called X-HDL3 at:
http://www.x-tekcorp.com/xhdl3.htm
There is a demo version that you can download,
to try out on your code, have a look at the
results, and make your own judgement about
how "good" it is for the code that you
are working on / with.

I have no affiliation with this company - it is
just a tool that I found.

From their website:
"This demo version is 100% functional except
that the source file size is restricted. Files larger
than the maximum size can be translated but the
output is restricted to viewing in a window only."

As well as having a close look at the VHDL
output, it would also be worthwhile synthesising
the output, using WebPACK / your preferred
synthesis tool.

Perhaps you could also search through fpga-faq
for some recommendations or comments about
translators
http://www.fpga-faq.com/

Best regards
Tony Burch
http://www.BurchED.com
FPGA boards, for System-On-Chip prototyping and education

----- Original Message -----
From: "Avi Ben-Moshe" <>
To: <>
Sent: Tuesday, 10 September 2002 2:41
Subject: [fpga-cpu] Verilog to VHDL tranlator > Hi,
> Can you recommend on a GOOD Verilog to VHDL translator?
> Thanks,
> Avi > To post a message, send it to:
> To unsubscribe, send a blank message to:




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RE: Verilog to VHDL tranlator - Avi Ben-Moshe - Sep 11 11:25:00 2002

Hi Tony,
Thank you for the information.
As you mentioned X-HDL3 gives a free demo, the problem is that all the files
that I've tried exceeded the allowed file size and all I get is a window
that I can't edit (copy etc.) so can't synthesize it and check if it works.
I have just one design that I want to translate so I don't want to spend so
much money for a translation tool that I will not use after that.
I found a free (or not expensive) tool that translates from VHDL to Verilog
but not the opposite.
If anybody knows and can recommend about a free Verilog to VHDL translator I
will be grateful.

Thanks,
Avi

-----Original Message-----
From: Tony Burch [mailto:]
Sent: Tuesday, September 10, 2002 1:28 AM
To:
Subject: Re: [fpga-cpu] Verilog to VHDL tranlator

Hi Avi,

There is a Verilog to VHDL, and VHDL to Verilog
translator called X-HDL3 at:
http://www.x-tekcorp.com/xhdl3.htm
There is a demo version that you can download,
to try out on your code, have a look at the
results, and make your own judgement about
how "good" it is for the code that you
are working on / with.

I have no affiliation with this company - it is
just a tool that I found.

>From their website:
"This demo version is 100% functional except
that the source file size is restricted. Files larger
than the maximum size can be translated but the
output is restricted to viewing in a window only."

As well as having a close look at the VHDL
output, it would also be worthwhile synthesising
the output, using WebPACK / your preferred
synthesis tool.

Perhaps you could also search through fpga-faq
for some recommendations or comments about
translators
http://www.fpga-faq.com/

Best regards
Tony Burch
http://www.BurchED.com
FPGA boards, for System-On-Chip prototyping and education

----- Original Message -----
From: "Avi Ben-Moshe" <>
To: <>
Sent: Tuesday, 10 September 2002 2:41
Subject: [fpga-cpu] Verilog to VHDL tranlator > Hi,
> Can you recommend on a GOOD Verilog to VHDL translator?
> Thanks,
> Avi > To post a message, send it to:
> To unsubscribe, send a blank message to: To post a message, send it to:
To unsubscribe, send a blank message to:




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xr16 lcc compiler issue? - Jeff Chang - Sep 12 21:56:00 2002

*************************************
--C source
--test.c

int main( ) {

int *po = (int*) 0xff40;
*po = 3;
return;
}

**************************************
-- asm code generated using lcc-xr16

# generated by xr16 rev.3 on Thu Sep 12 22:49:36 2002

addr code disassembly source
---- ---- ----------- ------
# file sim.s
; sim.s -- Simple
simulator startup code
; Copyright (C) 2000,
Gray Research LLC. All rights reserved.
; Usage subject to XSOC
License Agreement. See the LICENSE file.

global _main

sim:
0000 D7FF imm 7FF0 lea sp,0x7ffE
0002 2D0E addi r13,r0,-2
0004 C001 call 0010 call _main
0006 A000 jal r0,0(r0) j 0 ; exit
simulator
# file test.s
; generated by lcc-xr16
rev.3 on Thu Sep 12 22:49:05 2002

global _main
0008 0000 add r0,r0,r0 align 16
000A 0000 add r0,r0,r0
000C 0000 add r0,r0,r0
000E 0000 add r0,r0,r0
_main:
0010 2DDE addi r13,r13,-2 addi sp,sp,-2
0012 DFF4 imm FF40 lea r9,0xff40
0014 2900 addi r9,r0,0
0016 3000 and r0,r0 sw r9,-2+2(sp)
0018 89D0 sw r9,0(r13)
001A 59D0 lw r9,0(r13) lw r9,-2+2(sp)
001C 2803 addi r8,r0,3 lea r8,3
001E 3000 and r0,r0 sw r8,(r9)
0020 8890 sw r8,0(r9)
L1:
0022 2DD2 addi r13,r13,2 addi sp,sp,2
0024 A0F0 jal r0,0(r15) ret

# file end.s
; end.s -- Simple
simulator epilog code
; Copyright (C) 2000,
Gray Research LLC. All rights reserved.
; Usage subject to XSOC
License Agreement. See the LICENSE file.

end:
******************************************************

Pls. check stack operation, it's obviously not
correct.
Is it a compiler bug?
__________________________________________________


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RE: xr16 lcc compiler issue? - Jan Gray - Sep 15 8:46:00 2002

> From: Jeff Chang [mailto:]
...
> int main( ) {
>
> int *po = (int*) 0xff40;
> *po = 3;
> return;
> }
...
> -- asm code generated using lcc-xr16
...
> global _main
> 0008 0000 add r0,r0,r0 align 16
> 000A 0000 add r0,r0,r0
> 000C 0000 add r0,r0,r0
> 000E 0000 add r0,r0,r0
> _main:
> 0010 2DDE addi r13,r13,-2 addi sp,sp,-2
> 0012 DFF4 imm FF40 lea r9,0xff40
> 0014 2900 addi r9,r0,0
> 0016 3000 and r0,r0 sw r9,-2+2(sp)
> 0018 89D0 sw r9,0(r13)
> 001A 59D0 lw r9,0(r13) lw r9,-2+2(sp)
> 001C 2803 addi r8,r0,3 lea r8,3
> 001E 3000 and r0,r0 sw r8,(r9)
> 0020 8890 sw r8,0(r9)
> L1:
> 0022 2DD2 addi r13,r13,2 addi sp,sp,2
> 0024 A0F0 jal r0,0(r15) ret
...
> Pls. check stack operation, it's obviously not
> correct.
> Is it a compiler bug?

While the code may not be pretty -- and off the top of my head, I'm not
sure why it feels a need to store the local r9 and reload it -- from a
correctness perspective, it seems fine to me. Here's a simulator run:

% xr16 sim.s ff40.s end.s -sim
1 0000 sim D7FF imm 7FF0
2 0002 sim+2 2D0E addi r13,r0,-2 r13=32766
3 0004 sim+4 C001 call 0010 call _main 0 0 0 r15=6
6 0010 _main 2DDE addi r13,r13,-2 r13=32764
7 0012 _main+2 DFF4 imm FF40
8 0014 _main+4 2900 addi r9,r0,0 r9=-192
9 0016 _main+6 3000 and r0,r0
10 0018 _main+8 89D0 sw r9,0(r13) [7FFC]=FF40
12 001A _main+10 59D0 lw r9,0(r13) FF40=[7FFC] r9=-192
14 001C _main+12 2803 addi r8,r0,3 r8=3
15 001E _main+14 3000 and r0,r0
16 0020 _main+16 8890 sw r8,0(r9) [FF40]=0003
18 0022 _main+18 2DD2 addi r13,r13,2 r13=32766
19 0024 _main+20 A0F0 jal r0,0(r15) ret sim+6 0
22 0006 sim+6 A000 jal r0,0(r0) pc=sim
15 instructions 24 cycles 1.600000 CPI

Note this line:
16 0020 _main+16 8890 sw r8,0(r9) [FF40]=0003

This reflects that the word value 0003 was stored to *(int*)0xFF40 as
desired.

Jan Gray, Gray Research LLC




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