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Discussion Groups | FPGA-CPU | PCI implementation using Xilinx FPGA
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
PCI implementation using Xilinx FPGA - wilton peter - Oct 9 21:24:00 2002
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Dear All, I'm considering to design a PCI interface card using Xilinx FPGA and now I'm choosing the suitable chips. Would appreciate very much could anyone here help to answer following questions: 1. What type FPGA is suitable for PCI implementation? Virtex or Virtex-E? 2. Will the configuration (the PROM) time for FPGA put any influence on the PCI bus? I have this concern because I was told some motherboard will not re-scan the PCI when reset. If this is the case, how to get through? 3. Any tips for the development? Awaiting your reply, With regards Wilton -- _______________________________________________ Get your free email from http://mail.usa.com "Free price comparison tool gives you the best prices and cash back!" http://www.bestbuyfinder.com/download.htm |
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RE: PCI implementation using Xilinx FPGA - Author Unknown - Oct 10 1:25:00 2002
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Hi Wilton, Please find my comments below -og -----Original Message----- From: wilton peter [mailto:] Sent: Donnerstag, 10. Oktober 2002 04:24 To: Subject: [fpga-cpu] PCI implementation using Xilinx FPGA >Dear All, >I'm considering to design a PCI interface card using Xilinx FPGA and now I'm choosing the >suitable chips. Would appreciate very much could anyone here help to answer following >questions: >1. What type FPGA is suitable for PCI implementation? Virtex or Virtex-E? og: You can use both types as well as Virtex2, VirtexPro, Spartan(?) & Spartan2. Only difference I can remember is that a VirtexE can only use 3.3V PCI pad cells, where the 'good old' Virtex can also work @ 5V. If it is planned to be a volume product you might consider device costs as well, VirtexE are not that expensive (compared same size and package) and a bit faster due to smaller technology == die size. So 66MHz timing is always difficult even in a VirtexE ! On the other hand voltages/power supply might be more difficult. > 2. Will the configuration (the PROM) time for FPGA put any influence on the PCI bus? og: No if you have configured your device in less then one second. That's the maximum time (according to PCI specification) a device is allowed to be quit / not available (some controller based implementations have the same problem with booting up first :-) >I have this concern because I was told some motherboard will not re-scan the PCI when reset. If >this is the case, how to get through? og: Yes, that's right and also not the fully truth :-): Right after reset release the only PCI device that need's to be functional is basically the southbridge/ISA bridge so that the CPU can fetch EPROM/Flash boot code. Then all the system tests (memory, ide, HDDs,...) are executed, that takes some time. Usually the BIOS shows something on the screen and then clears the screen in order to show a table with all the detailed information (which CPU, how any mem aso). And this screen clear is the point in time the PCI enumeration takes place. Here your device need's to be functional. Also most of the OS do there own PCI enumeration at boot up (Windows since W95, Linux,...) even if in most cases the enumeration values are taken the BIOS has done. >3. Any tips for the development? Yeep, before you start schematics entry/PCB work have a look in the Xilinx ucf files (that come with the core) for the LOC constrains (pin assignments). It is recommended to use exactly these pins in order to easily meet timing and relax par effort, however I would not recommend to support 66MHz if not absolutely necessary! >Awaiting your reply, >With regards >Wilton -- _______________________________________________ Get your free email from http://mail.usa.com "Free price comparison tool gives you the best prices and cash back!" http://www.bestbuyfinder.com/download.htm To post a message, send it to: To unsubscribe, send a blank message to: --------------------------------- Gesendet von http://mail.yahoo.de. Möchten Sie mit einem Gruß antworten? http://grusskarten.yahoo.de. |
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RE: PCI implementation using Xilinx FPGA - wilton peter - Oct 10 8:27:00 2002
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Hi og, Thanks your kind help very much. I'm still not quite sure about the chip selection. My preferred one is Virtex-E since it is cheaper, is it safe to say, V-e can only work in 3.3v PCI? Can I connect the V-E pins to the PCI bus directly, or should I have some pull-up resistors to these pins? Sorry for the silly question but I didn't use the Virtex-E before. Many thanks again, Wilton ----- Original Message ----- From: Date: Thu, 10 Oct 2002 08:25:59 +0200 To: Subject: RE: [fpga-cpu] PCI implementation using Xilinx FPGA > > Hi Wilton, > > Please find my comments below > > -og > > -----Original Message----- > > From: wilton peter [mailto:] > > Sent: Donnerstag, 10. Oktober 2002 04:24 > > To: > > Subject: [fpga-cpu] PCI implementation using Xilinx FPGA > > >Dear All, > > >I'm considering to design a PCI interface card using Xilinx FPGA and now I'm choosing the > > >suitable chips. Would appreciate very much could anyone here help to answer following > > >questions: > > >1. What type FPGA is suitable for PCI implementation? Virtex or Virtex-E? > > og: You can use both types as well as Virtex2, VirtexPro, Spartan(?) & Spartan2. Only difference I can remember is that a VirtexE can only use 3.3V PCI pad cells, where the 'good old' Virtex can also work @ 5V. If it is planned to be a volume product you might consider device costs as well, VirtexE are not that expensive (compared same size and package) and a bit faster due to smaller technology == die size. So 66MHz timing is always difficult even in a VirtexE ! On the other hand voltages/power supply might be more difficult. > > > 2. Will the configuration (the PROM) time for FPGA put any influence on the PCI bus? > > og: No if you have configured your device in less then one second. That's the maximum time (according to PCI specification) a device is allowed to be quit / not available (some controller based implementations have the same problem with booting up first :-) > > >I have this concern because I was told some motherboard will not re-scan the PCI when reset. If >this is the case, how to get through? > > og: Yes, that's right and also not the fully truth :-): Right after reset release the only PCI device that need's to be functional is basically the southbridge/ISA bridge so that the CPU can fetch EPROM/Flash boot code. Then all the system tests (memory, ide, HDDs,...) are executed, that takes some time. Usually the BIOS shows something on the screen and then clears the screen in order to show a table with all the detailed information (which CPU, how any mem aso). And this screen clear is the point in time the PCI enumeration takes place. Here your device need's to be functional. Also most of the OS do there own PCI enumeration at boot up (Windows since W95, Linux,...) even if in most cases the enumeration values are taken the BIOS has done. > > >3. Any tips for the development? > > Yeep, before you start schematics entry/PCB work have a look in the Xilinx ucf files (that come with the core) for the LOC constrains (pin assignments). It is recommended to use exactly these pins in order to easily meet timing and relax par effort, however I would not recommend to support 66MHz if not absolutely necessary! > > >Awaiting your reply, > > >With regards > > >Wilton > > -- > > _______________________________________________ > > Get your free email from http://mail.usa.com > > "Free price comparison tool gives you the best prices and cash back!" > > http://www.bestbuyfinder.com/download.htm > > To post a message, send it to: > > To unsubscribe, send a blank message to: > > > > > --------------------------------- > Gesendet von http://mail.yahoo.de. > Möchten Sie mit einem Gruß antworten? http://grusskarten.yahoo.de. > To post a message, send it to: > To unsubscribe, send a blank message to: > > > -- _______________________________________________ Get your free email from http://mail.usa.com "Free price comparison tool gives you the best prices and cash back!" http://www.bestbuyfinder.com/download.htm |
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RE: PCI implementation using Xilinx FPGA - Author Unknown - Oct 10 8:48:00 2002
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Please find my comments below Oliver > -----Original Message----- > From: wilton peter [mailto:] > Sent: Thursday, October 10, 2002 3:28 PM > To: > Subject: RE: [fpga-cpu] PCI implementation using Xilinx FPGA > Hi og, > > Thanks your kind help very much. I'm still not quite sure > about the chip selection. My preferred one is Virtex-E since > it is cheaper, is it safe to say, V-e can only work in 3.3v > PCI? Yes: Xilinx datasheet says explicitly: absolute maximum voltage 4.0V (or so) So in a 'strong' 5V system (wrt driver strength) you might damage the device, no guarantee at all :-[ !!! >Can I connect the V-E pins to the PCI bus directly, or > should I have some pull-up resistors to these pins? Pull-up or ~down resistors would violate PCI spec (at least on a plug in card)! On most PCI system's are 5V pull up's on the motherboard. All newer PC-motherboards (I have seen) have the pull up's and driving 3.3V actively from the chipset devices (these are also 3.3V devices). But 3.3V driving voltage (even on a 5V bus) is sufficient according to PCI spec :-) ! > Sorry for > the silly question but I didn't use the Virtex-E before. > > Many thanks again, > > Wilton > ----- Original Message ----- > From: > Date: Thu, 10 Oct 2002 08:25:59 +0200 > To: > Subject: RE: [fpga-cpu] PCI implementation using Xilinx FPGA > > > > Hi Wilton, > > > > Please find my comments below > > > > -og > > > > -----Original Message----- > > > > From: wilton peter [mailto:] > > > > Sent: Donnerstag, 10. Oktober 2002 04:24 > > > > To: > > > > Subject: [fpga-cpu] PCI implementation using Xilinx FPGA > > > > > > > > >Dear All, > > > > >I'm considering to design a PCI interface card using > Xilinx FPGA and now I'm choosing the > > > > >suitable chips. Would appreciate very much could anyone > here help to answer following > > > > >questions: > > > > >1. What type FPGA is suitable for PCI implementation? > Virtex or Virtex-E? > > > > og: You can use both types as well as Virtex2, VirtexPro, > Spartan(?) & Spartan2. Only difference I can remember is that > a VirtexE can only use 3.3V PCI pad cells, where the 'good > old' Virtex can also work @ 5V. If it is planned to be a > volume product you might consider device costs as well, > VirtexE are not that expensive (compared same size and > package) and a bit faster due to smaller technology == die > size. So 66MHz timing is always difficult even in a VirtexE ! > On the other hand voltages/power supply might be more difficult. > > > > > > > > > 2. Will the configuration (the PROM) time for FPGA put > any influence on the PCI bus? > > > > og: No if you have configured your device in less then one > second. That's the maximum time (according to PCI > specification) a device is allowed to be quit / not available > (some controller based implementations have the same problem > with booting up first :-) > > > > >I have this concern because I was told some motherboard > will not re-scan the PCI when reset. If >this is the case, > how to get through? > > > > og: Yes, that's right and also not the fully truth :-): > Right after reset release the only PCI device that need's to > be functional is basically the southbridge/ISA bridge so that > the CPU can fetch EPROM/Flash boot code. Then all the system > tests (memory, ide, HDDs,...) are executed, that takes some > time. Usually the BIOS shows something on the screen and then > clears the screen in order to show a table with all the > detailed information (which CPU, how any mem aso). And this > screen clear is the point in time the PCI enumeration takes > place. Here your device need's to be functional. Also most of > the OS do there own PCI enumeration at boot up (Windows since > W95, Linux,...) even if in most cases the enumeration values > are taken the BIOS has done. > > > > > > > > >3. Any tips for the development? > > > > Yeep, before you start schematics entry/PCB work have a > look in the Xilinx ucf files (that come with the core) for > the LOC constrains (pin assignments). It is recommended to > use exactly these pins in order to easily meet timing and > relax par effort, however I would not recommend to support > 66MHz if not absolutely necessary! > > > > >Awaiting your reply, > > > > >With regards > > > > >Wilton > > > > -- > > > > _______________________________________________ > > > > Get your free email from http://mail.usa.com > > > > "Free price comparison tool gives you the best prices and > cash back!" > > > > http://www.bestbuyfinder.com/download.htm > > > > > > > > To post a message, send it to: > > > > To unsubscribe, send a blank message to: > > > > > > > > > > > > > > > > > > > > > --------------------------------- > > Gesendet von http://mail.yahoo.de. > > Möchten Sie mit einem Gruß antworten? http://grusskarten.yahoo.de. > > > > > > To post a message, send it to: > > To unsubscribe, send a blank message to: > > > > > > > > > > > > > -- > _______________________________________________ > > Get your free email from http://mail.usa.com > > "Free price comparison tool gives you the best prices and cash back!" > > http://www.bestbuyfinder.com/download.htm > > To post a message, send it to: > To unsubscribe, send a blank message to: > > > |
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