how to declare global variables in a package | FPGA-CPU

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hi everybody i have some small problem related vhdl programming. I have to convert C code to vhdl code on xilinx platform. In the c code one program consisting of all functions and in that begining of program they declared "overflow" and "carry" as global to that program i.e it is global to all functions of that program. so for that to convert into vhdl i just wrote one package in that package declaration i declared all the functions and in that package body iwrote function defnitions.now in some functions i am changing "carry" and "overflow values" then these values shold reflect whole packaga. i tried with this pattern work.packagename.signal name by declaring carry and overflow in another package and including this package into package consisting of functions.... can any one please suggest a way declare these two "carry"and "overflow".... thanking u all bye gupta ksrc ---------------------------------

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how to declare global variables in a package - gupta ksrc - Oct 29 22:31:00 2002