Sign in

username:

password:



Not a member?

Search fpga-cpu



Search tips

Subscribe to fpga-cpu



fpga-cpu by Keywords

Altera | CISCifying | IDE | ISA | Java | JHDL | JTAG | LBU | MicroBlaze | PAR | PCI | RISC | SoC | Spartan | Transputers | Verilog | VHDL | Virtex | VLIW | WebPack | Xilinx | Xsoc | YARD-1A

Discussion Groups

Discussion Groups | FPGA-CPU | LEON Verilog simulation

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

LEON Verilog simulation - howlingmadwilger - Nov 1 6:51:00 2002


I'm a final year computer science student at the University of
Bristol, England. I am currently doing research for my final year
project titled "Writing an instruction stream generator for a DUV".

Currently, I am having problems finding a DUV. Could anyone tell me
where I could find a LEON Verilog simulation?

Much appreciated,

Howling Mad Wilger.





(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )

RE: LEON Verilog simulation - Jeffery, Robert - Nov 1 11:03:00 2002

Hi Howling.

As far as I am aware there is only a VHDL model for the Leon design. Check
out the following sites.

http://www.gaisler.com/
http://www.leox.org/

Cheers.

Robert.

-----Original Message-----
From: howlingmadwilger [mailto:]
Sent: 01 November 2002 11:52
To:
Subject: [fpga-cpu] LEON Verilog simulation I'm a final year computer science student at the University of
Bristol, England. I am currently doing research for my final year
project titled "Writing an instruction stream generator for a DUV".

Currently, I am having problems finding a DUV. Could anyone tell me
where I could find a LEON Verilog simulation?

Much appreciated,

Howling Mad Wilger.
To post a message, send it to:
To unsubscribe, send a blank message to:



(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )

RE: LEON Verilog simulation - Jan Gray - Nov 1 11:04:00 2002

1. Please define DUV for us.
2. There is a *VHDL* model for LEON SPARC at
http://www.gaisler.com/main.html.
3. What does a "DUV" have to do with LEON SPARC?

Jan Gray, Gray Research LLC




(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )