Sign in
Search fpga-cpu
Subscribe to fpga-cpu
fpga-cpu by Keywords
Altera | CISCifying | IDE | ISA | Java | JHDL | JTAG | LBU | MicroBlaze | PAR | PCI | RISC | SoC | Spartan | Transputers | Verilog | VHDL | Virtex | VLIW | WebPack | Xilinx | Xsoc | YARD-1A
Ads
Discussion Groups
Discussion Groups | FPGA-CPU | FPGA multiprocessors & OO VHDL
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
FPGA multiprocessors & OO VHDL - adityadatey - Nov 29 17:12:00 2002
|
Hi! im new to this grp and a newbie in comp arch. Work has been done on single chip multiprocessors using FPGAs from what i read. Id like to know more in these areas.. are these FPGAs programmed using standard VHDL? What kind of message passing network is used? How good is OO VHDL? if we make every processor in the chip an object (assuming we're doing the coding in OO VHDL) can the message passing facility of OO VHDL be used instead of whatevers being used right now? in short..can we apply OO concepts like message passing (instead of signals & ports etc) and design a programmable multiprocessor? thankx.. |
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )