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Discussion Groups | FPGA-CPU | Ann: IO expansion with Ethernet chip
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Ann: IO expansion with Ethernet chip - Martin Schoeberl - Dec 8 13:06:00 2002
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Some weeks ago I announced an ACEX prototyping board. Now an IO expansion for this is
available. The board contains CS8900 Ethernet chip, voltage regulator and EMC/ESD protected IO. The main purpose for this board was to build a complete Internet enabled system with JOP (my Java Processor). But it can also be usefull if you need a simple solution to play around with Ethernet in your FPGA projects. More info: http://www.jopdesign.com/board.html Sources for CS8900 driver and a simple TCP/IP stack are available in Java. For analog input you can find a VHDL file for simple sigma delta ADC. Kind regards Martin Schoeberl [Non-text portions of this message have been removed] |
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