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Discussion Groups | FPGA-CPU | [AD] Altera Cyclone FPGA board
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
[AD] Altera Cyclone FPGA board - Martin Schoeberl - Feb 24 16:43:00 2003
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The first (or one of the first :-) Cyclon prototyping board is available. Altera anounces the combination of Cyclone and Nios as a Low-Cost SOPC Solution. But for me SOPC means CPU, logic and memory in one chip. CPU is (as you know in this group) no problem, but current FPGAs still lack in the memory area. Internal RAM is too small for larger programs and there is no Flash in the FPGA. The new board compensates this with an extern three stage memory hirarchy: fast asynchron memory as main memory (conventional) Flash for coniguration data and application (big) NAND Flash for solide state disc The board is a module compatible to Jopcore. An expansion board with Ethernet connection (Basio) is also available for both boards. The Facts: Altera Cyclone EP1C6Q240C8 FPGA step down voltage regulator (1V5) crystal clock (20 MHz) 512KB Flash (for FPGA configuration and program) up to 1MB fast async Ram up to 128MB NAND Flash byteblaster port watchdog with led EPM7064 PLD to load FPGA from flash (on watchdog reset) serial interface (MAX3232) 56 general IO pins The RAM consists of two independent 16 Bit banks (with own address and control lines). Both RAM chips are on the back side of the PCB direct under the FPGA pins. The traces are very short (below 10 mm) so it is possible to use the RAMs at full speed without reflection problems. The two banks can be combined to form 32 Bit RAM or support two independent CPU cores (A dual processor system in an FPGA :-). When Altera ships the EP1C12 the same board will also be availabe with them. Further information: http://www.jopdesign.com/cyclone/index.jsp Kind regards Martin Schoeberl [Non-text portions of this message have been removed] |
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Re: [AD] Altera Cyclone FPGA board - Tommy Thorn - Feb 24 19:52:00 2003
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Martin Schoeberl wrote: > I prefere async SRAM for cpu designs. I don't like the long 'setup' time for > the DDR. DDR is fine if you transfer a larger block of data (like fill the > cach) but is slow for random access. Absolutely, but DDR SDRAM has several orders of magnitude more capacity (that I'd need for my applications). I find efficient use of SDRAM to be a most interesting problem. Ideally you'd have both, fx. using SRAM for instructions and SDRAM for data with a L1 data cache made out of BRAM. >>Risking opening a can of worms, which Spartan-IIE compares to EP1C12? > > You're not opening a can of worms, because you only sent your comments to me > personal. If you want send it to the group use: . > I would like to see your comment in the group :-) I found part of the answer to my question in a mail from Jan Gray to this list: Look for September 23 in http://www.fpgacpu.org/log/sep02.html In short: EP1C6 80 Kb BRAM, 6 KLUT XC2S300E 64 Kb BRAM, 6 KLUT EP1C12 208 Kb BRAM, 12 KLUT So, an EP1C12 looks like a capable device, comparable to an XC2S600E (not listed), but with more BRAM. I wonder how the speed compares. Also, while the free Xilinx Web Pack only supports up to Spartan IIE XC2S300E (and some Virtex), the free Quartus II supports all of the Cyclone devices (http://www.altera.com/products/software/pld/products/quartus2/sof-quarwebmain.html). I've only worked with Xilinx, so it'll take some energy to get started with Altera, but I might try it when EP1C12 becomes available. >>Finally, I was unable to read the FirstSteps.doc. A PDF version would >>be much appreciated. > > Ok, done. I've converted it to a PDF: > http://www.jopdesign.com/cyclone/FirstSteps.pdf Thanks, Tommy PS: You should get your cyclone board listed on http://www.fpga-faq.com/FPGA_Boards.htm |
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Re: [AD] Altera Cyclone FPGA board - Martin Schoeberl - Feb 24 20:23:00 2003
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> Martin Schoeberl wrote: > > I prefere async SRAM for cpu designs. I don't like the long 'setup' > time for > > the DDR. DDR is fine if you transfer a larger block of data (like > fill the > > cach) but is slow for random access. > > Absolutely, but DDR SDRAM has several orders of magnitude more capacity > (that I'd need for my applications). I find efficient use of SDRAM to > be a most interesting problem. Ideally you'd have both, fx. using SRAM > for instructions and SDRAM for data with a L1 data cache made out of > BRAM. How much memory do you need? And whats your application? > I found part of the answer to my question in a mail from Jan Gray to > this list: Look for September 23 in http://www.fpgacpu.org/log/sep02.html > In short: > > EP1C6 80 Kb BRAM, 6 KLUT > XC2S300E 64 Kb BRAM, 6 KLUT > EP1C12 208 Kb BRAM, 12 KLUT It's good to have two big players in this field. (Better than the Wintel situation) > So, an EP1C12 looks like a capable device, comparable to an XC2S600E > (not listed), but with more BRAM. I wonder how the speed compares. I think it will be in the same range, and it depends on the speed grade. The Cylone devices are really new, so not all speed grades are availble now. And we're waiting for the EP1C12 :-) > Also, while the free Xilinx Web Pack only supports up to Spartan IIE > XC2S300E (and some Virtex), the free Quartus II supports all of the > Cyclone devices > (http://www.altera.com/products/software/pld/products/quartus2/sof-quarwebma in.html). Yeah, that's cool. But Altera has also some problems getting the tools working with the newest chips. You need the latest service pack to generate program files and I had problems with post route simulation of a design (JOP the Java processor) for Cyclone. But I got it running without the simulation... > I've only worked with Xilinx, so it'll take some energy to get started > with Altera, but I might try it when EP1C12 becomes available. I worked most of the time (for years) with Altera. But that has only historic reasons. Once a time I bougth a Xilinx board from Burch and played around with it a little bit. > PS: You should get your cyclone board listed on > http://www.fpga-faq.com/FPGA_Boards.htm Will do that! As you can see the predecessor (a board with Alter ACEX) is listed. Martin |
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