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This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
VHDL and Verilog - Jin Yan - Feb 25 12:53:00 2003
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Hi, everyone, I am new in this field. Could somebody kindly tell me which one, VHDL or Verilog, is commonly used in industry? Or which language is suitable to what kind of application? I am choosing one language to do fpga programming and wondering the pros and cons of these two languages in industry and their usage. Thank you very much. Yan __________________________________________________ |
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Re: VHDL and Verilog - Tommy Thorn - Feb 25 13:06:00 2003
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Jin Yan wrote: > I am new in this field. Could somebody kindly tell me > which one, VHDL or Verilog, is commonly used in > industry? Or which language is suitable to what kind > of application? > > I am choosing one language to do fpga programming and > wondering the pros and cons of these two languages in > industry and their usage. I'm sure there are as many opinions about this as subscribers to this mailing list. Did you even _try_ looking for the answer on the Net? Just googling "VHDL vs. Verilog" found tons of links. IMHO: Both are similar. VHDL is more verbose, slightly higher level, has better better static checking. It's no accident that Verilog looks like C and VHDL looks like Ada. VHDL has some features (eg, generate) that are not available in VHDL, but it's easy (and common) to use a some kind of frontend or macro processor to achieve the same. Both are used in industry, but I think Verilog might be a little more widespread. I'm not a big fan of either, but I use Verilog (can't stand verbosity). /Tommy |
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AW: VHDL and Verilog - Kolja Sulimma - Feb 25 13:16:00 2003
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AFAIK VHDL is predominant in Europe and Verilog is very common in the USA. In looks lik VHDL is gaining ground in the US, too. But Tommy is right: Your VHDL code will be significantly larger than your Verilog code. Kolja Sulimma -----Ursprüngliche Nachricht----- Von: Tommy Thorn [mailto:] Gesendet: Dienstag, 25. Februar 2003 19:06 An: Betreff: Re: [fpga-cpu] VHDL and Verilog Jin Yan wrote: > I am new in this field. Could somebody kindly tell me > which one, VHDL or Verilog, is commonly used in > industry? Or which language is suitable to what kind > of application? > > I am choosing one language to do fpga programming and > wondering the pros and cons of these two languages in > industry and their usage. I'm sure there are as many opinions about this as subscribers to this mailing list. Did you even _try_ looking for the answer on the Net? Just googling "VHDL vs. Verilog" found tons of links. IMHO: Both are similar. VHDL is more verbose, slightly higher level, has better better static checking. It's no accident that Verilog looks like C and VHDL looks like Ada. VHDL has some features (eg, generate) that are not available in VHDL, but it's easy (and common) to use a some kind of frontend or macro processor to achieve the same. Both are used in industry, but I think Verilog might be a little more widespread. I'm not a big fan of either, but I use Verilog (can't stand verbosity). /Tommy To post a message, send it to: To unsubscribe, send a blank message to: |
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Re: AW: VHDL and Verilog - Tommy Thorn - Feb 25 13:27:00 2003
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Kolja Sulimma wrote: > AFAIK VHDL is predominant in Europe and Verilog is very common in the > USA. Although this is a FAQ I'm glad it came up again as it made me check some of the ABOUNDANT articles on the issue. I'll especially recommend this one: http://www.cl.cam.ac.uk/users/mjcg/Verilog/Cooley-Verilog-Won In summary, from googling it seems that the Net almost unanimously favours Verilog. Glad to hear that I chose right :-) Oh, and the "not available in VHDL" should had been "not available in Verilog" of course. Sorry about that, > In looks lik VHDL is gaining ground in the US, too. Interesting. Do you have any data to support that claim? > But Tommy is right: Your VHDL code will be significantly larger than > your Verilog code. Something else I didn't mention. I initially tried to learn both, but found Verilog to be much easier to learn and understand. Eventually I just stopped bothering with VHDL. /Tommy > > Kolja Sulimma > > -----Ursprüngliche Nachricht----- > Von: Tommy Thorn [mailto:] > Gesendet: Dienstag, 25. Februar 2003 19:06 > An: > Betreff: Re: [fpga-cpu] VHDL and Verilog > Jin Yan wrote: > > I am new in this field. Could somebody kindly tell me > > which one, VHDL or Verilog, is commonly used in > > industry? Or which language is suitable to what kind > > of application? > > > > I am choosing one language to do fpga programming and > > wondering the pros and cons of these two languages in > > industry and their usage. > > I'm sure there are as many opinions about this as subscribers to this > mailing list. Did you even _try_ looking for the answer on the Net? > Just googling "VHDL vs. Verilog" found tons of links. > > IMHO: > > Both are similar. VHDL is more verbose, slightly higher level, has > better better static checking. It's no accident that Verilog looks like > C and VHDL looks like Ada. > > VHDL has some features (eg, generate) that are not available in VHDL, > but it's easy (and common) to use a some kind of frontend or macro > processor to achieve the same. > > Both are used in industry, but I think Verilog might be a little more > widespread. > > I'm not a big fan of either, but I use Verilog (can't stand verbosity). > > /Tommy > > To post a message, send it to: > To unsubscribe, send a blank message to: > > > > > > To post a message, send it to: > To unsubscribe, send a blank message to: > > |
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AW: AW: VHDL and Verilog - Kolja Sulimma - Feb 25 13:42:00 2003
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> > In looks lik VHDL is gaining ground in the US, too. > Interesting. Do you have any data to support that claim? Nope. This is just my impression from talking to CAD vendors and users at conferences. > > But Tommy is right: Your VHDL code will be significantly larger than > > your Verilog code. > Something else I didn't mention. I initially tried to learn both, but > found Verilog to be much easier to learn and understand. Eventually I > just stopped bothering with VHDL. Agreed. In theory VHDL is a lot more flexible, but you never need that flexibility. It only gives you a hard time when you want to do simple things. And in VHDL you spend most of your time figuring how to cast your datatypes. (Exagerated) I am using VHDL anyway, because I am in an VHDL environment. Kolja Sulimma |
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