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Discussion Groups | FPGA-CPU | OFFTOPIC How to know in VHDL the simulation time?

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

OFFTOPIC How to know in VHDL the simulation time? - Perez Ramas, Javier Basilio - Mar 4 9:36:00 2003



Hi,

I wish to make an off-topic VHDL question. I want to apologise myself before do it because I know that this isn't the best place to place it.

I want to make the actual simulation time in VHDL. I don't know if this is possible and how to do it, but it seems to me that this would be a very logical feature for the testbenches.

I'm talking about something similar to ... variable t:time;

...

t:=actual_simulation_time(); Best regards,

Javier Basilio





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