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Discussion Groups | FPGA-CPU | verilog to vhdl

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

verilog to vhdl - eesha_78 - Mar 12 22:26:00 2003

i'm very new in this area. i want to know how to convert from verilog
to vhdl language..for example

assign a= &b[7:0];
assign c= |d[7:0];

when i try to convert to vhdl..

a= and b(7 downto 0);
c or d(7 downto 0);

but there was an error..
what & and | in front of b and d is meant
i hope someone can help me.
thanks




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Re: verilog to vhdl - Dries Driessens - Mar 13 2:42:00 2003

as far as my vhdl knowledge reaches, in vhdl there aren't any similar
instructions.
the only thing that would definitely work:

FIRST POSSIBILITY:
a='1';
for (i in 7 downto 0) loop
a = a AND b(i);
end loop;
(same principle for or)

SECOND POSSIBILITY:
if (b = "11111111") then
a = '1';
else
a = '0';
end if;

if (c = "00000000") then
d = '0';
else
d = '1';
end if; when you hate to use "00..0", there is a way to create constants.
i can give an example if you want.

eesha_78 wrote:

>i'm very new in this area. i want to know how to convert from verilog
>to vhdl language..for example
>
>assign a= &b[7:0];
>assign c= |d[7:0];
>
>when i try to convert to vhdl..
>
>a= and b(7 downto 0);
>c or d(7 downto 0);
>
>but there was an error..
>what & and | in front of b and d is meant
>i hope someone can help me.
>thanks >To post a message, send it to:
>To unsubscribe, send a blank message to: >.




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Re: verilog to vhdl - Dries Driessens - Mar 13 3:02:00 2003

shamsiah suhaili wrote:

>can u explain more....
>in verilog if the if instruction is a condition
IF ...condition... (is thrue than) ...reaction for true... ELSE
...reaction for false...

>assign a= &b[7:0];
>
>it mean every bit of b is consider until it get 1 bit
>answer. am i right?
>
???
b = "11111111" => a = '1'
b = "01111111" => a = '0'
b = "11101001" => a = '0'

>now i want to change it and using vhdl..
>can u give me more example..
>
FIST EXAMPLE:

a='1'; -- if you don't do this, you will get a = '0' as a result every time

for (i in 7 downto 0) loop -- the system will loop this 8 times (for every bit once)
a = a AND b(i); -- every bit is being AND
end loop;

---------------------------------------------------------------------------------------------------------------------------------------

SECOND EXAMPLE:

if (b = "11111111") then --
a = '1';
else
a = '0';
end if; >thanks >__________________________________________________
>
>.




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RE: verilog to vhdl - Perez Ramas, Javier Basilio - Mar 13 5:59:00 2003

IEEE offers a very useful and elegant set of logic reduction functions in the std_logic_misc package

A<=AND_REDUCE(b);
A<=OR_REDUCE(b);
etc...

Best regards -----Mensaje original-----
De: Dries Driessens [mailto:]
Enviado el: jueves, 13 de marzo de 2003 8:42
Para:
Asunto: Re: [fpga-cpu] verilog to vhdl as far as my vhdl knowledge reaches, in vhdl there aren't any similar
instructions.
the only thing that would definitely work:

FIRST POSSIBILITY:
a='1';
for (i in 7 downto 0) loop
a = a AND b(i);
end loop;
(same principle for or)

SECOND POSSIBILITY:
if (b = "11111111") then
a = '1';
else
a = '0';
end if;

if (c = "00000000") then
d = '0';
else
d = '1';
end if; when you hate to use "00..0", there is a way to create constants.
i can give an example if you want.

eesha_78 wrote:

>i'm very new in this area. i want to know how to convert from verilog
>to vhdl language..for example
>
>assign a= &b[7:0];
>assign c= |d[7:0];
>
>when i try to convert to vhdl..
>
>a= and b(7 downto 0);
>c or d(7 downto 0);
>
>but there was an error..
>what & and | in front of b and d is meant
>i hope someone can help me.
>thanks >To post a message, send it to:
>To unsubscribe, send a blank message to: >.
To post a message, send it to:
To unsubscribe, send a blank message to:



(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )