This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
|
Hi Mr. Jan Gray I'm trying to implement a systolic array on a Virtex FPGA. The number of inputs is limited, hence I decided to use deterministic bit stream arithmetic ( IEEE trans on Neural Networks page 1514 (i think May) 2002). Can you help me with information regarding stochastic/deterministic bit stream arithmetic implementations on FPGAs? Thanks, Sagar |