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Discussion Groups | FPGA-CPU | Regarding Xilinx CORE Generator and Mentor FPGA adv
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Regarding Xilinx CORE Generator and Mentor FPGA adv - abhishek_is_online - Mar 14 3:57:00 2003
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Hi, I want to build some blocks for my modem design using Xilinx cores. Moreover i am using the FPGA advantage package (VHDL) for designing my modem. I imported xilinx's ISE 4.2 Xilinxcorelib into FPGA advantage, and I could simulate my cores in ModelSim. The problems comes when i synthesize using Leonardo spectrum, which is not synthesizing the cores due to errors, most probably due to some xilinx specific VHDL language constructs. If someone has worked on similar tools, and succesfully synthesized the cores,and could help me out, I would be grateful to him / her. Thanks and regards, Abhishek Mitra |
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RE: Regarding Xilinx CORE Generator and Mentor FPGA adv - Perez Ramas, Javier Basilio - Mar 17 6:34:00 2003
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Hi Abhishek, The Xilinx COREs aren't written in VHDL. The VHDL that the Core Generator provides is only for simulation purpouses. You must exclude that VHDL of your project and do the synthesis with your tool, who will identify the component as a black box. Then, while doing the mapping with Xilinx ISE, the Xilinx tool will incorporate the core. The CORE generator cores are provided as RPM macros. Best regards, Javier Basilio -----Mensaje original----- De: abhishek_is_online [mailto:] Enviado el: viernes, 14 de marzo de 2003 9:57 Para: Asunto: [fpga-cpu] Regarding Xilinx CORE Generator and Mentor FPGA adv Hi, I want to build some blocks for my modem design using Xilinx cores. Moreover i am using the FPGA advantage package (VHDL) for designing my modem. I imported xilinx's ISE 4.2 Xilinxcorelib into FPGA advantage, and I could simulate my cores in ModelSim. The problems comes when i synthesize using Leonardo spectrum, which is not synthesizing the cores due to errors, most probably due to some xilinx specific VHDL language constructs. If someone has worked on similar tools, and succesfully synthesized the cores,and could help me out, I would be grateful to him / her. Thanks and regards, Abhishek Mitra To post a message, send it to: To unsubscribe, send a blank message to: |
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