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This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
XSOC/xr16 running on Virtex - Jan Gray - Oct 11 0:41:00 2000
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This afternoon I resumed the Virtex port of XSOC/xr16/xr32 and am now (finally) running XSOC/xr16 in my XESS XSV-300 prototyping board. Today's work involved several compromises. Since this board does not have a tool to pre-load the SRAM, I modified the XSOC design to provide a 256x16 boot ROM in a block RAM. I further modified the new fully synchronous MEMCTRL so that instruction fetches from this block RAM signal RDY in the same cycle. Just as with the XSOC/xr16 kit for XS40 boards, the design currently includes a bitmapped VGA display, using the DMA engine in the xr16 CPU core as the video address counter. (With a 50 MHz dot clock, it refreshes the display at 120 Hz!) Alas the XSV's two 16-bit SRAM banks both lack byte-write-enables. For the time being I am using just one byte-wide bank of SRAM. Later I will modify MEMCTRL to perform read-modify-write accesses for byte stores to RAM, Using a modified version of xr16 (replacing the double-cycled single-port RAMs in the regfiles with dual-port RAMs), we get a design that TRCE reports will run at 60 MHz in a V300-5. (Not floorplanned yet.) Total size of the design, including MEMCTRL and VGA, is about 400 logic cells. The design runs fine at 33 MHz. At 50 MHz, the program runs fine, but accesses to the external SRAM frame buffer fail. I will therefore modify the memory controller to insert a wait state on each external SRAM access. That done, I should be able to tune up the core design up to 67 MHz in short order, motivating integrated instruction and data caches... Jan Gray Gray Research LLC |
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