SOS on coprocessors | FPGA-CPU | EmbeddedRelated.com

hi guys, I'm looking to interface an fpga coprocessor to a main processor like a PC or SUN workstation.Are there any regular off the shelf products(devlopment boards and tools) for the same or do i have to develop my own interface using PCI etc.Any easy solutions available on this ?? do hlp me out sriram wrote:To post a message, send it to: To unsubscribe, send a blank message to: ------------------------------------------------------------------------ There are 8 messages in this issue. Topics in this digest: 1. What are peoples opinion of the Altera Nios Processor? From: "barrem23" 2. Re: What are peoples opinion of the Altera Nios Processor? From: kannaiah badam 3. Re: What are peoples opinion of the Altera Nios Processor? From: Dries Driessens 4. RE: Regarding Xilinx CORE Generator and Mentor FPGA ad v From: "Jeffery, Robert" 5. RE: What are peoples opinion of the Altera Nios Processor? From: "Josh Pfrimmer" 6. Re: What are peoples opinion of the Altera Nios Processor? From: Christian Plessl 7. RE: Data Modified Code From: "Perez Ramas, Javier Basilio" 8. Re: What are peoples opinion of the Altera Nios Processor? From: "Martin Schoeberl" ________________________________________________________________________ ________________________________________________________________________ Message: 1 Date: Mon, 17 Mar 2003 23:23:16 -0000 From: "barrem23" Subject: What are peoples opinion of the Altera Nios Processor? What kind of problems have you experienced? How was there support? If you could do it again would you use the NIOS processor? ________________________________________________________________________ ________________________________________________________________________ Message: 2 Date: Tue, 18 Mar 2003 04:07:00 +0000 (GMT) From: kannaiah badam Subject: Re: What are peoples opinion of the Altera Nios Processor? We have tried NIOS ver 1.0 ON WIN98. ver 1.0 was horrible with win98, informed ALTERA application engineers, but not succussful. Altera requested to upgrade to MSWIN2000 with NIOS update version. The new version is fine and we are happy with it. Since the is not responding, we have to get clarifications in debugging c routines. b.kannaiah --- wrote: > What kind of problems have you experienced? How was > there support? > If you could do it again would you use the NIOS > processor? > > To post a message, send it to: > > To unsubscribe, send a blank message to: > > > ________________________________________________________________________ Missed your favourite TV serial last night? Try the new, Yahoo! TV. visit http://in.tv.yahoo.com ________________________________________________________________________ ________________________________________________________________________ Message: 3 Date: Tue, 18 Mar 2003 08:45:33 +0100 From: Dries Driessens Subject: Re: What are peoples opinion of the Altera Nios Processor? barrem23 wrote: >What kind of problems have you experienced? > We had one problem with the VHDL-synthesis-flow. After synthesis with Synplify, we couldn't place & route with Quartus. That was because SOPC Builder generated low-level stuff in the VHDL specifically for your component. The solution was selecting FLEX components in SOPC Builder. >How was there support? > An FAE from France helped us out. >If you could do it again would you use the NIOS processor? > All depends. If you want high performance, choose a seperate processor-IC. If you have a complex FPGA design, and you have some room left on your FPGA, choose Nios, Microblaze, Leon Sparc of OpenRisc. If you're developing a high-volume ASIC. Choose Leon Sparc or OpenRisc. If you're developing a mid-volume ASIC. Choose Nios or Microblaze on Cyclone/Spartan or Hardcopy devices. Maybe even the next generation gate array from Nec or LSI with a Leon Sparc or OpenRisc. If you're developing a low-volume ASIC, you live in the past ;-) > > >To post a message, send it to: >To unsubscribe, send a blank message to: >. ________________________________________________________________________ ________________________________________________________________________ Message: 4 Date: Tue, 18 Mar 2003 12:07:02 -0000 From: "Jeffery, Robert" Subject: RE: Regarding Xilinx CORE Generator and Mentor FPGA ad v Hi Abhishek. This sort of issue should be dealt with through the software vendor or a newsgroup that deals with these sorts of issues. The FPGA-CPU group is for questions on CPU's in FPGA's. If you have a support contract with Mentor Graphics they can help you with this kind of problem or you can use the Mentor Graphics SupportNet services to help you. Goto www.mentor.com as a starting point. If you want to use Xilinxcorelib parts in FPGA Advantage use the integrated CoreGen icon in HDL Designer (See the online help and in the index search for coregen). This will then import the CoreGen part into the HDL Designer database along with the EDIF layout file. You need to have a compiled version of the Xilinxcorelib library. Details of this process are in appnote 1823 but again the support folk should be able to help you with this. Cheers. Robert. -----Original Message----- From: abhishek_is_online [mailto:] Sent: 14 March 2003 08:57 To: Subject: [fpga-cpu] Regarding Xilinx CORE Generator and Mentor FPGA adv Hi, I want to build some blocks for my modem design using Xilinx cores. Moreover i am using the FPGA advantage package (VHDL) for designing my modem. I imported xilinx's ISE 4.2 Xilinxcorelib into FPGA advantage, and I could simulate my cores in ModelSim. The problems comes when i synthesize using Leonardo spectrum, which is not synthesizing the cores due to errors, most probably due to some xilinx specific VHDL language constructs. If someone has worked on similar tools, and succesfully synthesized the cores,and could help me out, I would be grateful to him / her. Thanks and regards, Abhishek Mitra To post a message, send it to: To unsubscribe, send a blank message to: ________________________________________________________________________ ________________________________________________________________________ Message: 5 Date: Tue, 18 Mar 2003 00:00:26 -0800 From: "Josh Pfrimmer" Subject: RE: What are peoples opinion of the Altera Nios Processor? Oooh... good topic for me (and in light of recent list politics, I sure hope it's interesting to some of you as well :) ) I'll be writing a paper in the next few weeks: a survey of commercially and freely available 32-bit RISC IP cores. For the paper, I'm interested in hard and soft cores, but for the future, my research will require one that I can customize (that is, VHDL or Verilog available). I'm already looking at LEON for that... but I'd appreciate input as well. Thanks Josh Pfrimmer, B.Eng _____ University of Victoria -----Original Message----- From: Dries Driessens [mailto:] Sent: March 17, 2003 11:46 PM To: Subject: Re: [fpga-cpu] What are peoples opinion of the Altera Nios Processor? We had one problem with the VHDL-synthesis-flow. After synthesis with Synplify, we couldn't place & route with Quartus. That was because SOPC Builder generated low-level stuff in the VHDL specifically for your component. The solution was selecting FLEX components in SOPC Builder. >How was there support? > An FAE from France helped us out. >If you could do it again would you use the NIOS processor? > All depends. If you want high performance, choose a seperate processor-IC. If you have a complex FPGA design, and you have some room left on your FPGA, choose Nios, Microblaze, Leon Sparc of OpenRisc. If you're developing a high-volume ASIC. Choose Leon Sparc or OpenRisc. If you're developing a mid-volume ASIC. Choose Nios or Microblaze on Cyclone/Spartan or Hardcopy devices. Maybe even the next generation gate array from Nec or LSI with a Leon Sparc or OpenRisc. If you're developing a low-volume ASIC, you live in the past ;-) ________________________________________________________________________ ________________________________________________________________________ Message: 6 Date: Tue, 18 Mar 2003 17:26:25 +0100 From: Christian Plessl Subject: Re: What are peoples opinion of the Altera Nios Processor? > I'll be writing a paper in the next few weeks: a survey of commercially and > freely available 32-bit RISC IP cores. Interssting. You may post a link to the paper to this group, when it is ready. > For the paper, I'm interested in hard and soft cores, but for the future, > my research will require one that I can customize (that is, VHDL or Verilog > available). I'm already looking at LEON for that... but I'd appreciate > input as well. We used LEON in some project, about a year ago. From the functional point LEON was ok, it worked well. The good point is, that LEON comes with a compiler/assembler toolchain that works out-of-the-box. The drawback of LEON on FPGAs is that it is quite large and pretty slow. We have synthesized LEON for a Xilinx Virtex XCV800-5, the maximum speed we could reach was about 25 MHz, the design used 3800 slices. I guess, we could have pushed this somewhat further by floorplanning, but 25 MHz was sufficient performance for our application. Compared to Microblaze, LEON is much larger and slower, but comparing them is not really fair, as Microblaze was specifically optimized for Virtex FPGAs. Best regards, Christian -- Christian Plessl Computer Engineering Lab (TIK), ETH Zurich, Switzerland ________________________________________________________________________ ________________________________________________________________________ Message: 7 Date: Tue, 18 Mar 2003 17:59:29 +0100 From: "Perez Ramas, Javier Basilio" Subject: RE: Data Modified Code Hi Rob, > -----Mensaje original----- > De: Rob Finch [mailto:] > Enviado el: s�bado, 26 de octubre de 2002 19:40 > Para: > Asunto: [fpga-cpu] Data Modified Code > Funny idea #9000 > > It's not really the executing code that determines what the > resulting data is; but it is really the data that determines what > the shape of the code to be executed is. In other words, we should > be using the data to build the code instead of using the code to > manipulate the data. > > Taking this viewpoint, would it be possible to do something like the > following ? I remember something similar to that called "systolic architectures" but I don't know of any real implementation. > When a method is called, take a snapshot of the dataset that is > available to the method and create a 'data signature' based on that > data. Perhaps using a hash algorithm that can run in hardware in > parallel with other operations. > > Then as the code for the method is executing, build an image of > which instructions are actually executing and build a 'code > signature' based on this image. And store the code signature and > it's image in a table. The table might only contain the displacement > of the next instruction to execute as opposed to the actual code > itself, or it might be encode using some more efficient means. > > Eventually the idea is to build a table of data signatures and their > corresponding code images / signatures. Then whenever a particular > data signature occurs, execute the corresponding code image instead > of executing the original code. Many different data signatures are > likely to result in the same code signature. > > The trick here is that the code images don't contain any conditional > branches, meaning it can probably be executed very fast... I've doubts about the efficency of that system. How would you manage the "code signatures"? I suppose that you should have a dedicated memory where you copy the code after executing each instruction. So if you want a real speed enhance the amount of memory should be enough larger to store a significative number of usual data signatures. And with a high number of signatures the "hash" algorithm would be too complicated. Also you should consider the frequency of calls to procedures with the same data. Is there any study about that? Best regards, Javier Basilio Indra Sistemas ________________________________________________________________________ ________________________________________________________________________ Message: 8 Date: Tue, 18 Mar 2003 18:10:25 +0100 From: "Martin Schoeberl" Subject: Re: What are peoples opinion of the Altera Nios Processor? > > I'll be writing a paper in the next few weeks: a survey of commercially and > > freely available 32-bit RISC IP cores. > > Interssting. You may post a link to the paper to this group, when it is ready. > > > For the paper, I'm interested in hard and soft cores, but for the future, > > my research will require one that I can customize (that is, VHDL or Verilog > > available). I'm already looking at LEON for that... but I'd appreciate > > input as well. > > We used LEON in some project, about a year ago. From the functional point LEON > was ok, it worked well. The good point is, that LEON comes with a > compiler/assembler toolchain that works out-of-the-box. The drawback of LEON > on FPGAs is that it is quite large and pretty slow. We have synthesized LEON > for a Xilinx Virtex XCV800-5, the maximum speed we could reach was about 25 > MHz, the design used 3800 slices. I guess, we could have pushed this > somewhat further by floorplanning, but 25 MHz was sufficient performance for > our application. Compared to Microblaze, LEON is much larger and slower, but > comparing them is not really fair, as Microblaze was specifically optimized > for Virtex FPGAs. A Java Processor is not a classical RISC processor, but as in my implementation it is a simple stack machine with a very small instruction set (reduced instruction set :-). It has 47 different instrcutions, all variations counted. So instructions can be coded in 8 bit WITH some operand. And it fits in an Altera ACEX 1K50, about 2000 LCs (depends on the periphery you use) and runns at about 30 MHz in the slowest speed grade. Did port it two weeks ago to Cyclone (yes a porting was necessary because of the different embedded memory), and Quartus says it should run at about 80 MHz. Interested? Martin Schoeberl ________________________________________________________________________ ________________________________________________________________________ ---------------------------------

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Discussion Groups | FPGA-CPU | SOS on coprocessors

SOS on coprocessors - sriram anand - Mar 20 14:03:00 2003

Re: SOS on coprocessors - Christian Plessl - Mar 23 17:14:00 2003