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This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
- sriram anand - Mar 24 22:21:00 2003
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hi chirstian, I tried several sites including xilinx but all supported only PC's,nothing for SUN.So the question still stands. thnx, sriram Date: Sun, 23 Mar 2003 23:14:45 +0100 From: Christian Plessl Subject: Re: SOS on coprocessors What did you try to find an answer yourself? Christian On Thursday 20 March 2003 20:03, sriram anand wrote: > hi guys, > > I'm looking to interface an fpga coprocessor to a main processor like a PC > or SUN workstation.Are there any regular off the shelf products(devlopment > boards and tools) for the same or do i have to develop my own interface > using PCI etc.Any easy solutions available on this ?? > > do hlp me out > > sriram -- Christian Plessl Computer Engineering and Networks Lab, ETH Zurich, Switzerland ________________________________________________________________________ ________________________________________________________________________ --------------------------------- |
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Re: (unknown) - Christian Plessl - Mar 25 3:12:00 2003
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On Tuesday 25 March 2003 04:21, sriram anand wrote: > hi chirstian, > I tried several sites including xilinx but all supported only PC's,nothing > for SUN.So the question still stands. thnx, > sriram There are plenty of PCI based FPGA boards, cf. http://www.fpga-faq.com/FPGA_Boards.htm I also don't know of any board that comes with SUN drivers out of the box. You will have to write your own drivers for most of the boards. Best regards, Christian -- Christian Plessl <> Computer Engineering Lab (TIK), ETH Zurich, Switzerland |
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Nios cache size - Josh Pfrimmer - Apr 11 19:29:00 2003
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I'm comparing some of the currently available 32-bit RISC cores... currently looking at the Altera Nios 3.0, but having some trouble finding all the information I'd like. Specifically Altera says that the cache size is "configurable" without giving any more details. Is there a maximum size (and some specified granularity), or is it simply a function of how much chip space you have? Also, can anyone shed some light on an equivalent gate count? I'm not familiar enough with LEs and EAB/ESB to compare the size of the Nios with, say, the MicroBlaze. (Altera reports ~3000 LE's, Xilinx reports ~1050 Virtex CLBs) Thanks. JP |
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Re: Nios cache size - jerry - Apr 12 3:25:00 2003
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> Altera Nios 3.0 I don't have 3.0 version - I have the one before 3.0 (it's AFAIR 2.2) > Specifically Altera says that the cache size is "configurable" without 2.2 doesn't have cache - it has only 5-stage pipeline. > giving any more details. Is there a maximum size (and some specified > granularity), or is it simply a function of how much chip space you > have? > > Also, can anyone shed some light on an equivalent gate count? I'm not using 'marketing' gates, so I can tell you only in terms of LEs: pure Nios 2.2 (without peripherals) uses 1500 LEs (depending on features: hardware multiply, pipeline optimisation, shifting, instruction decoder as ROM, etc). > familiar enough with LEs and EAB/ESB to compare the size of the Nios > with, say, the MicroBlaze. (Altera reports ~3000 LE's, Xilinx > reports ~1050 Virtex CLBs) If you can compare chips, it would be easier to compare uC. Basic Nios configuration (core, tristate-bridge, uart, 32bit I/O port and timer) uses 25% of EP20K200E and runs for 55MHz without careful optimisation (it's possible to make Nios >80MHz but I haven't done it). Compare it to 'equivalent' from brand-X. jerry "The day Microsoft makes something that doesn't suck is probably the day they start making vacuum cleaners." - Ernst Jan Plugge |
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