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Discussion Groups | FPGA-CPU | Calling a verilog-like package from VHDL
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Calling a verilog-like package from VHDL - shaik afzal - May 28 1:49:00 2003
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Hi all, Hope this is not an off-topic query. We have a set of VHDL Design files(Say VHDL1.Vhd,VHDL2.vhd etc.) and a VHDL Package(VHDL_pack.vhd) file. VHDL Design files(VHDL1.Vhd,VHDL2.vhd etc) and VHDL Package (VHDL_pack.vhd) file is converted to equivalent veriog design files(Say , Ver1.v,Ver2.v etc.) and the verilog Package(Ver_pkg.v) file. One way by which verilog-like Package(Ver_pkg.v) file is referred in the veriog design files(Say ,Ver1.v,Ver2.v etc.) using the statement 'include "Ver_pkg.v" and not using module statements ; Second way by which verilog-like Package(Ver_pkg.v) file is referred in the veriog design files(Say ,Ver1.v,Ver2.v etc.) is as explained in http://www.model.com/resources/tips_tricks/verilog_package.asp. These two methods works succesfully when we call Ver_pkg.v from a verilog file. But calling a "Ver_pkg.v" from a VHDL file (Here Testenv.Vhd) is not working successfully as we can gauge from the line # ** Error: src_work/testenv.vhd(13): Unknown field: Ver_pkg. # ** Error: src_work/testenv.vhd(16): VHDL Compiler exiting Is there any solution for this.. Thanks Best Regards SHaik Afzal |
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Re: Calling a verilog-like package from VHDL - Ed Corter - May 28 12:19:00 2003
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If the VHDL modules are tested and qualified.. I would, not convert to them verilog..... - I would synthesize the VHDL code into an EDIF...... either a generic edif path for a flexible destination technology or a 'Target Device Specific edif path' - Instantiate ( in Verilog ) a black box to represent ports for the VHDL ,synthesized, netlist. ........... The black box may need directives.... I dont trust tools, let alone a 'VHDL 2 Verilog cvtr.. ', to properly implement designs. You should verify the design, at the technology level, to ensure that either process had correct results... 'Technology Level' is the design as it will appear in the ( Mapped, translated and P&R'd ) target devices resources.... LUT's, FF, CLB's etc... If need help with edif generation for BBox use or a bbox example with directives.... email me @ the address in this page http://ca.geocities.com/artiedc/index.htm Ed --------------------------------- |
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