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Discussion Groups | FPGA-CPU | altera cyclone bitstream format ?

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

altera cyclone bitstream format ? - __--__ - Jun 23 17:26:00 2003


** I am attempting to get information about the altera bitstream format **

I have already read

http://opencollector.org/news/Bitstream/

I wanted to make sure I wasn't missing something, is the information for
creating bitstreams for altera cyclone devices publicly available?

I would like to create some software akin to JBITS for the altera devices
and can't seem to locate the exact format specifications.

Ideally one could create designs in other HLLs w/o having to target VHDL
or Verilog for synthesis. Having to parse one HLL and convert it into VHDL
for synthesis greatly complicates the construction of the tool chain.

What process do the altera "partners" have to go through for getting this
information? Is it simply an NDA or is there money involved?

-- curious george



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