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Discussion Groups | FPGA-CPU | Re: Digest Number 512

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

Re: Digest Number 512 - Sagar Sen - Jul 6 7:20:00 2003


Hi Gian

try the virtex 1 or 2 memory rich architecture.

Sagar
On Sun, 06 Jul 2003 wrote :
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>------------------------------------------------------------------------
>
>There is 1 message in this issue.
>
>Topics in this digest:
>
> 1. multiCPUs + wide bus on FPGA
> From: "Gianluca" < >________________________________________________________________________
>________________________________________________________________________
>
>Message: 1
> Date: Sat, 5 Jul 2003 01:18:53 +0100
> From: "Gianluca" <>
>Subject: multiCPUs + wide bus on FPGA
>
>Dear all
>
>I am interested in FPGA prototyping. So far I practiced some FPGA
>design using Altera Quartus II 2.2 but I still have to touch with
>hand a real FPGA device.
>
>My project is implementing a multi CPUs architecture composed by
>CPUs with integer ALUs and few registers connected by a 16bit
>(minimum) memory buses to their own ram through a L1 common
>cache. A dedicated data bus will link each CPU to the others.
>
>At this stage I want keep the design to a minimum of simplicity
>in order to fit it into a FPGA and also early complexity may
>discourage me.
>
>This project is meant to be a PCI mounted accelerator for a
>specific set of instructions.
>
>I would like to know how much of such a project may fit on a
>FPGA, if yes what will be the best choice to start ? if not what
>could I use instead of a FPGA ?
>How wide can a memory bus be ?
>
>Thank you for your help.
>Gian >
>[Non-text portions of this message have been removed] >
>
>________________________________________________________________________
>________________________________________________________________________ >

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