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Discussion Groups | FPGA-CPU | GR0000 -- yet another simple FPGA CPU core, a work-in-progress
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
GR0000 -- yet another simple FPGA CPU core, a work-in-progress - Jan Gray - Oct 22 11:14:00 2000
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One evening last August, I sketched out the Verilog for a new, simpler RISC processor, simpler and smaller than xr16. (I mentioned this in http://www.egroups.com/message/fpga-cpu/109.) Like xr16, it is designed to be the target of lcc and has 16-bit instructions, 16-bit data, and 16 registers. Unlike xr16, (but like Brian Davis's YARD-1A), it is a 2-operand architecture, is not pipelined, and uses a single bank of dual-port RAM for the register file. Initially it will use the Virtex-family block-RAM as the instruction store. The goals are to provide a simple, fully embeddedable MCU, comparable to KCPSM but C programmable, and to advance the agenda of demystifying processor design and encouraging student and enthusiast experimentation. (In retrospect, the pipelining of xr16 is good for performance but detracts from its simplicity.) I will be presenting this CPU/SoC design at an upcoming design conference. Like XSOC/xr16, it is "disclosed source", licensed under the XSOC LICENSE agreement. Taking a page from the "literate programming" community, the write-up of the design is the design. Using Microsoft Word, I save the document as text and filter that to extract the Verilog source. Here is the current work-in-progress in PDF [http://www.fpgapcu.org/gr0000-draft-001021.pdf] (The processor is mostly sketched out but it surely doesn't compile yet.) "Processor and SoC design is not rocket science ... To prove the point, this paper and accompanying 50-minute class will present the complete design and implementation of a streamlined, but real, system-on-a-chip and FPGA RISC processor." Jan Gray Gray Research LLC |
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Re: GR0000 -- yet another simple FPGA CPU core, a work-in-progress - Leon Heller - Oct 23 12:50:00 2000
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>work-in-progress in PDF [http://www.fpgapcu.org/gr0000-draft-001021.pdf] There seems to be aproblem with the above link. BTW, I've ordered a couple of Virtex chips, and I'll be designing a simple PCB to put them on, if anyone is interested. It'll have a couple of LED displays, DIL switch, pushbuttons, clock, and VGA I/F. Download via the Xilinx parallel cable. Regards, Leon -- Leon Heller, G1HSM Tel (work): +44 1327 357824 Tel (mobile): +44 79 9098 1221 InfraRed Integrated Systems Ltd., Towcester Mill, Towcester, Northants., NN12 6AD, United Kingdom. Email: Web page: http://www.geocities.com/SiliconValley/Code/1835 _________________________________________________________________________ Get Your Private, Free E-mail from MSN Hotmail at http://www.hotmail.com. Share information about yourself, create your own public profile at http://profiles.msn.com. |
Stellaris® MCU Family: New Parts, New Package, New Price.
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Re: GR0000 -- yet another simple FPGA CPU core, a work-in-progress - Author Unknown - Oct 23 19:18:00 2000
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>BTW, I've ordered a couple of Virtex chips, and I'll be designing a simple >PCB to put them on, if anyone is interested. It'll have a couple of LED >displays, DIL switch, pushbuttons, clock, and VGA I/F. Download via the >Xilinx parallel cable. > >Regards, >Leon > >-- >Leon Heller, G1HSM >Tel (work): +44 1327 357824 Tel (mobile): +44 79 9098 1221 >InfraRed Integrated Systems Ltd., Towcester Mill, Towcester, Northants., >NN12 6AD, United Kingdom. >Email: >Web page: http://www.geocities.com/SiliconValley/Code/1835 I haven't announced this anywhere else yet, but I thought it may be of benefit, in case it can save anyone from unneccesarily incurring the expense of doing their own PCB. I realise some users will be set on using Virtex instead of Spartan II, but it's hard to go past Spartan II's price... I will be releasing a Spartan II 200K gate FPGA Prototyping Kit, called BED-SPARTAN2+, in about three weeks. There are also some "add-on kits" that will be released at the same time, some of which will be of interest to FPGA-CPUers. For example the BED-FPGA-CPU-IO (including RS232, VGA, PS2, K/B), and BED-SRAM (128K x 16) kits. These plug straight onto the headers on the BED-SPARTAN2+ kit. The BED-SPARTAN2+ Kit will come fully assembled (so you don't have to worry about soldering the PQ208 package yourself). It will be shipped with a CDROM with the latest release of the Xilinx WebPack software that will support Spartan II. Target price for the kit at this stage is US$120. This kit is the next generation on from our current range of kits, which can be seen at www.BurchED.com.au The current Xilinx one is at http://www.burched.com.au/bedxilinxbase.html It is US$60. We aim to provide the lowest cost, easiest to use FPGA Prototyping Kits. Regards Tony Burch www.BurchED.com.au |
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Re: GR0000 -- yet another simple FPGA CPU core, a work-in-progress - Mike Butts - Oct 23 21:58:00 2000
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>work-in-progress in PDF [http://www.fpgapcu.org/gr0000-draft-001021.pdf] > ^^^ > There seems to be aproblem with the above link. http://www.fpgacpu.org/gr0000-draft-001021.pdf By the way, I applaud all of you putting boards together. The Insight board is a good start but falls short on high-speed I/O. --Mike |
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