This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
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Hello Group-members, I wanted a suggestion from you all regarding implementing a CPU on FPGA. This project is to be carried out by an electronics engineering graduate, and after completion of the project he is supposed to know most of the CPU technologies like pipelining, instruction-prefetch, cache management, etc. Which CPU is best suited to know all these? Your expert comments are very much needed. Regards, Srinath |
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Why not pick the XR16? It is well documented and designed for FPGA implementation. Perhaps set your student to optimise if for one thing or make it 32 bit or add DMA (think about it as jam loading an instruction) - something where he/she can start from a known working design but need to understand what has been done to extended it (which is why the DMA is nice, becuase one has to think of the effect on interrupts etc). Otherwise, pick a small RISC cpu. -- Veronica Merryfield, somewhere in Cambridgeshire, UK "Constructive laziness is the root of all good engineering" "The best things in life aren't things" Do not wish to be anything but what you are, and try to be that perfectly. - St. Francis De Sales www.dunrunnin.co.uk www.greyhoundgap.com www.yadvashem.org.il - Everyone should visit ----- Original Message ----- From: "Srinath Bagal V" <> To: <> Sent: Saturday, October 18, 2003 10:44 AM Subject: [fpga-cpu] a good processor for implementation.. > Hello Group-members, > > I wanted a suggestion from you all regarding implementing a CPU on FPGA. This > project is to be carried out by an electronics engineering graduate, and > after completion of the project he is supposed to know most of the CPU > technologies like pipelining, instruction-prefetch, cache management, etc. > Which CPU is best suited to know all these? Your expert comments are very > much needed. > > Regards, > Srinath > > To post a message, send it to: > To unsubscribe, send a blank message to: |
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Please go through the ALTERA, NIOS soft processor. visit www.altera.com All the best badam kannaiah --- Srinath Bagal V <> wrote: > Hello Group-members, > > I wanted a suggestion from you all regarding > implementing a CPU on FPGA. This > project is to be carried out by an electronics > engineering graduate, and > after completion of the project he is supposed to > know most of the CPU > technologies like pipelining, instruction-prefetch, > cache management, etc. > Which CPU is best suited to know all these? Your > expert comments are very > much needed. > > Regards, > Srinath > > To post a message, send it to: > > To unsubscribe, send a blank message to: > > > ________________________________________________________________________ Yahoo! India Matrimony: Find your partner online. Go to http://yahoo.shaadi.com |
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> I wanted a suggestion from you all regarding implementing a CPU on FPGA. This
> project is to be carried out by an electronics engineering graduate, and > after completion of the project he is supposed to know most of the CPU > technologies like pipelining, instruction-prefetch, cache management, etc. > Which CPU is best suited to know all these? Which textbooks are you planning to use? How much do they know about logic design and implementation beforehand, or is this also intended to be part of the course? For the computer architecture, there is really only one choice, the outstanding John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach. This book covers all the issues in computer architectures in depth, including the ones you mention above. The working example is the MIPS32 architecture, which is THE classic RISC architecture and would a good choice for your students. Not only is this probably the best documented and most studied RISC architectures, it's also very well supported by tools (gcc, binutils, gdb) and libraries (newlib). Nothing is more motivating than being able to run actual programs on your new implementation. Implementing the classic five stage integer pipeline should be within the reach of your students and there is plenty of room for going beyond that (big caches, deeper pipeline, dynamic scheduling, super scalar, etc). Regards, Tommy |
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Hi Veronica... "Constructive laziness is the root of all good engineering" Is that yours? If so, can I nick it (with attribution of course!) for my sigmonster? Thanks, Martin -- Martin Thompson CEng MIEE TRW Conekt Stratford Road, Solihull, B90 4AX. UK Tel: +44 (0)121-627-3569 - |
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It's mine :) Too many years of practising engineering (I will get it right one day) and watching (Managing) others. Sure you can nick it :) Talking of managing, another one for you "Managing software engineers is like trying to herd cats". -- Veronica Merryfield, somewhere in Cambridgeshire, UK "Constructive laziness is the root of all good engineering" "The best things in life aren't things" Do not wish to be anything but what you are, and try to be that perfectly. - St. Francis De Sales www.dunrunnin.co.uk www.greyhoundgap.com www.yadvashem.org.il - Everyone should visit ----- Original Message ----- From: "Martin.J Thompson" <> To: <> Sent: Monday, October 20, 2003 8:35 AM Subject: Re: [fpga-cpu] a good processor for implementation.. > Hi Veronica... > > "Constructive laziness is the root of all good engineering" > > Is that yours? If so, can I nick it (with attribution of course!) for my sigmonster? > > Thanks, > Martin > > -- > Martin Thompson CEng MIEE > TRW Conekt > Stratford Road, Solihull, B90 4AX. UK > Tel: +44 (0)121-627-3569 - > To post a message, send it to: > To unsubscribe, send a blank message to: |
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Dear Group-members, Thanks one and all for all your suggestion. By the way, this is a project work which is the part of the course. They know RTL coding. Regards, Srinath On Saturday 18 October 2003 23:15, you wrote: > > I wanted a suggestion from you all regarding implementing a CPU on FPGA. > > This project is to be carried out by an electronics engineering graduate, > > and after completion of the project he is supposed to know most of the > > CPU technologies like pipelining, instruction-prefetch, cache management, > > etc. Which CPU is best suited to know all these? > > Which textbooks are you planning to use? How much do they know about > logic design and implementation beforehand, or is this also intended > to be part of the course? > > For the computer architecture, there is really only one choice, the > outstanding John L. Hennessy and David A. Patterson, Computer > Architecture: A Quantitative Approach. > > This book covers all the issues in computer architectures in depth, > including the ones you mention above. The working example is the > MIPS32 architecture, which is THE classic RISC architecture and would > a good choice for your students. > > Not only is this probably the best documented and most studied RISC > architectures, it's also very well supported by tools (gcc, binutils, > gdb) and libraries (newlib). Nothing is more motivating than being > able to run actual programs on your new implementation. Implementing > the classic five stage integer pipeline should be within the reach of > your students and there is plenty of room for going beyond that (big > caches, deeper pipeline, dynamic scheduling, super scalar, etc). > > Regards, > > Tommy > > To post a message, send it to: > To unsubscribe, send a blank message to: > |
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Hi all, Can someone recommend some website with example on existing microprocessor coding in Verilog and the steps needed to complete the coding. If got step by step the better as I really got no idea to start the coding except by first drawing out the block diagram first. But what I really do after that? I really hope someone can guide me as I'm really new to coding in HDL. I think a better way to learn is to see how others have done and the way others did it as this is my first project on HDL. Thank you all....... Regards, Khoo Eng How E&E undergraduate --------------------------------- |