Sign in
Search fpga-cpu
Subscribe to fpga-cpu
fpga-cpu by Keywords
Altera | CISCifying | IDE | ISA | Java | JHDL | JTAG | LBU | MicroBlaze | PAR | PCI | RISC | SoC | Spartan | Transputers | Verilog | VHDL | Virtex | VLIW | WebPack | Xilinx | Xsoc | YARD-1A
Ads
Discussion Groups
Discussion Groups | FPGA-CPU | How Input & OutputFile Use in testbench in VHDL!
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
How Input & OutputFile Use in testbench in VHDL! - nastaran mmmmm - Nov 3 11:05:00 2003
|
How can I use of Inputfile & Outputfile(TEXTIO) in testbench in VHDL. I download and study all of documents from internet. Thus, I need a sample program that include main modul and its testbench in VHDL. I have foundation ISE Thank you --------------------------------- |
|
|
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: How Input & OutputFile Use in testbench in VHDL! - rohit kumar - Nov 3 23:52:00 2003
|
check this site, www.acc-eda.com/vhdlref/refguide/language_overview/test_benches/ reading_and_writing_files_with_text_i_o.htm regards rohit nastaran mmmmm <> wrote: How can I use of Inputfile & Outputfile(TEXTIO) in testbench in VHDL. I download and study all of documents from internet. Thus, I need a sample program that include main modul and its testbench in VHDL. I have foundation ISE Thank you --------------------------------- To post a message, send it to: To unsubscribe, send a blank message to: --------------------------------- |
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )