Sign in

Search fpga-cpu

Subscribe to fpga-cpu

fpga-cpu by Keywords

Discussion Groups

Discussion Groups | FPGA-CPU | Need help with Insight Spartan2-100 FPGA board

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

Need help with Insight Spartan2-100 FPGA board - Author Unknown - Nov 5 0:02:00 2000

I just got an Insight Spartan2-100 FPGA board which I hope to do some simple RISC-CPU work on. Unfortunately, I can't get the darn thing to work! I'm trying to get the simple 'demo-counter' working. I'm using Foundation Express 2.1i SP6 (I'm fairly familiar with Foundation Express, so I'm confident I make a newbie mistake, like not connecting the clk, reset, I/O pads, etc.) But I have no experience with the Xilinx parallel III download cable (came with my company's Foundation Express.) I've tried connecting cable to both the JTAG and the 'JP6' connector (as stated in the Insight documentation.) I was careful to connect all pins, including the VCC and GND pin. If I try to program with "Hardware Debugger" (set to use LPT1), the download process seems to execute ok, but at the end I receive an error message "Device is not configured. DONE is not high." There is one cable wire labelled 'D/P'. I'm guessing this is connected to DONE. (I tried the other connecting the wire to other board pins, like INIT and RST...both cause an error-message which prevents the Xilinx software from attempting to download.) If I try the JTAG progammer (again set to LPT1), I get some long-winded error message " ... Loading Boundary-Scan Description Language (BSDL) file 'C:/Fndtn/spartan2/data/xc2s100_pq208.bsd'.....completed successfully. Checking boundary-scan chain integrity...ERROR:JTag - Boundary-scan chain test failed at bit position '4' on instance 'test0002(Device1)'. Check that the cable, system and device JTAG TAP connections are correct, that the boundary-scan chain configuration specified matches the actual hardware, that the target system power supply is set to the correct level, that the system grounds are connected and that the parts are properly decoupled. ERROR:JTag - Boundary scan chain has been improperly specified. Please check your configuration and re-enter the boundary-scan chain information. Boundary-scan chain validated unsuccessfully. ERROR:JTag - : The boundary-scan chain has not been declared correctly. Verify the syntax and correctness of the device BSDL files, correct the files, reset the cable and retry this command. ... I'm totally stuck! I'm certain the parallel port on my PC works fine. My HP deskjet prints fine, and I can download to an Xess XS-40 board, using Xess's parallel cable, just fine. (Note, I only connect one cable at a time. I'm not using a splitter box or other parallel port extender.)

(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )

RE: Need help with Insight Spartan2-100 FPGA board - Lee Ainscough - Nov 6 3:09:00 2000

This might not be the answer, but I have had the same symptoms when I connected the Din and Clk pins the wrong way round. This might not the be the cause of the problem on your board. Good luck with sorting it out. Lee > -----Original Message----- > From: [SMTP:] > Sent: Sunday, November 05, 2000 5:03 AM > To: > Subject: [fpga-cpu] Need help with Insight Spartan2-100 FPGA board > > I just got an Insight Spartan2-100 FPGA board which I hope to do some > simple RISC-CPU work on. > > Unfortunately, I can't get the darn thing to work! I'm trying to get > the simple 'demo-counter' working. I'm using Foundation Express 2.1i > SP6 (I'm fairly familiar with Foundation Express, so I'm confident I > make a newbie mistake, like not connecting the clk, reset, I/O pads, > etc.) > > But I have no experience with the Xilinx parallel III download cable > (came with my company's Foundation Express.) I've tried connecting > cable to both the JTAG and the 'JP6' connector (as stated in the > Insight documentation.) I was careful to connect all pins, including > the VCC and GND pin. > > If I try to program with "Hardware Debugger" (set to use LPT1), the > download process seems to execute ok, but at the end I receive an > error message "Device is not configured. DONE is not high." > There is one cable wire labelled 'D/P'. I'm guessing this is > connected to DONE. (I tried the other connecting the wire to other > board pins, like INIT and RST...both cause an error-message which > prevents the Xilinx software from attempting to download.) > > If I try the JTAG progammer (again set to LPT1), I get some > long-winded error message " > > ... > > Loading Boundary-Scan Description Language (BSDL) file > 'C:/Fndtn/spartan2/data/xc2s100_pq208.bsd'.....completed successfully. > Checking boundary-scan chain integrity...ERROR:JTag - Boundary-scan > chain test failed at bit position '4' on instance 'test0002(Device1)'. > Check that the cable, system and device JTAG TAP connections > are correct, > that the boundary-scan chain configuration specified matches > the actual hardware, > that the target system power supply is set to the correct > level, > that the system grounds are connected and that the parts are > properly decoupled. > ERROR:JTag - Boundary scan chain has been improperly specified. > Please check your configuration and re-enter the boundary-scan chain > information. > Boundary-scan chain validated unsuccessfully. > ERROR:JTag - : The boundary-scan chain has not been declared > correctly. > Verify the syntax and correctness of the device BSDL files, > correct the files, > reset the cable and retry this command. > > ... > > I'm totally stuck! I'm certain the parallel port on my PC works > fine. My HP deskjet prints fine, and I can download to an Xess XS-40 > board, using Xess's parallel cable, just fine. (Note, I only connect > one cable at a time. I'm not using a splitter box or other parallel > port extender.) > > To Post a message, send it to: > To Unsubscribe, send a blank message to:

(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )