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Discussion Groups | FPGA-CPU | Re: BGA prototype Bypassing
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Re: BGA prototype Bypassing - Ed Corter - Feb 6 3:00:00 2004
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Of course not..... But - the wires that power the VCC rings were stabilized with larger low ERS caps. - at every Red and White wire ( IO & Core vcc connects ) there is are .01 & .1 uF caps connecting from the vcc ring to the gnd ring. Without a real PCB this was as close to the Power & Gnd Grid Balls I could manage. Stability: Clock into the Virtex is 45 mHz For the Initial test of the board: - a 2x DLL was implemented and all four of it's 1\4 cycle duty outputs were were brought out to general purpose IO and inspected on an oscilloscope (450mHz). Signals were inspected for, both, jitter and level noise. All was great ! The next test had Xilinx's Chipscope ILA (integrated Logic Analyzer) instantiated along side of a homebrew, statemachine based UART... This used the JTAG port ILA along with a running design and everything seemed stable. I.E. the ILA never triggered from any glitches. PS if anyone wants the Verilog for the UART it's my code and free to all http://ca.geocities.com/artiedc/files/UartZip.zip --------------------------------- |
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