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Discussion Groups | FPGA-CPU | XSOC VGA controller

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

XSOC VGA controller - Author Unknown - Nov 5 20:42:00 2000

I was thinking about modifying the VGA-controller on the XSOC chip,
to
enable a full blown alphanumeric display (fancy language for 'text
display'!) But I wondered, anybody else already working on something
similar?

All I've done so far, is rip font-tables from my VGA-BIOS. I wrote a
simple C DOS-program to call the VGA_BIOS for pointers to the various
loaded fonts, then I copy the contents memory location to a
binary file. It only works with 8-pixel wide fonts (8x8, 8x14,
8x16.)
I was a bit lazy and didn't feel like adding the bit-manipulation
routines to make it work with 9-pixel wide fonts (9x14, 9x16.)






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Re: XSOC VGA controller - Author Unknown - Nov 15 1:12:00 2000

--- In , liaor@h... wrote:
> I was thinking about modifying the VGA-controller on the XSOC chip,
> to
> enable a full blown alphanumeric display (fancy language for 'text
> display'!) But I wondered, anybody else already working on
something
> similar?

I have finished a Verilog HDL prototype of the alphanumeric display
controller. The controller is a simple '80x30 text display', at a
base pixel resolution of 640x480 (character cell-size=8H X 16V.) The
vertical font-size is user-changeable by altering parameter and
resynthesizing. The horizontal size is fixed at 8. And of course,
the CRTC timers can be changed to create non-standard text-screen
sizes, with some restrictions. I don't have HDL simulation
capability, so I did the next best thing and synthesized it to my
XS40-010XL+ :)

The design occupies more logic than i'd hoped. On the other hand, I
did design it to run fast, with standard synchronous (posedge)
flipflops. On a XC4010XL-3, XSE 2.1i reports the design will run at
least 50MHz. This was the result of overly pipelining (more so than
needed with an ASIC technology) every step of sync-timing generation,
framebuffer fetch address calculation, and character font address
calculation.

On an XS40-010XL+ v1.4, the design runs fine at 25MHz. I budgeted two
cycles per memory access, translating into a bandwidth requirement of
50%! (Every 8 clocks, there is 1 fetch for the text-screen, and 1
more fetch for font-data. This means the display-controller consumes
4 out of 8 available memory clocks.) I ripped the font-bitmap from my
VGA BIOS (using a simple Turbo C++ DOS program to query MSDOS
interrupt 0x10.) This provides a 256 ANSI-character set (4KByte.)

At 50MHz, I see a lot of 'twinkling glitches' on screen, some sort of
failure. My *theory* : the controller logic works, but access to
XS40's SRAM is the failure path.

I'll polish this some more and then try to integrate this into the
(XSOC 093Beta) schematic distribution. I'll probably have to trim
down some logic to make it fit.

(Incidentally, I was unable to successfully synthesize the Verilog
version of XSOC. XSE 2.1i comes close to, but can't seem to meet the
timing constraints.) > All I've done so far, is rip font-tables from my VGA-BIOS. I wrote a
> simple C DOS-program to call the VGA_BIOS for pointers to the
various
> loaded fonts, then I copy the contents memory location to a
> binary file. It only works with 8-pixel wide fonts (8x8, 8x14,
> 8x16.)
> I was a bit lazy and didn't feel like adding the bit-manipulation
> routines to make it work with 9-pixel wide fonts (9x14, 9x16.)



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