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This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
FPGA DESIGN - Avinash Shetty - Mar 19 15:26:00 2004
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hi .... i just bought a DIGILINT Xilinx FPGA Board D2/Dio2 https://digilent.us/Sales/Product.cfm?Prod=D2 https://digilent.us/Sales/Product.cfm?Prod=DIO2 ....i have no problems in writeing the code in Verilog or VHDL ....but i am not at all familiar as to how to download and mainly how to configure the board as in .ucf file ...the board has several 7 segment displays ,LCD Panel and switches ...Please guide me as to how i can connect my design to get these things working ...what data sheets to see ..what pin numbers to connect ....if there is a tutorial which explains all this ...it would be great ... Regards Avinash |
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Re: FPGA DESIGN - Animesh Pathak - Apr 9 16:15:00 2004
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Your ID says that you go to USC. In that case, meet prog. Gandhi Puvvada of EE department. He can guide you on this. Thanks Animesh Grad. Student, EE Systems, USC --- In , Avinash Shetty <avi_trojan@y...> wrote: > hi .... > i just bought a DIGILINT Xilinx FPGA Board D2/Dio2 > https://digilent.us/Sales/Product.cfm?Prod=D2 > https://digilent.us/Sales/Product.cfm?Prod=DIO2 > > ....i have no problems in writeing the code in Verilog or VHDL ....but i am not at all familiar as to how to download and mainly how to configure the board as in .ucf file ...the board has several 7 segment displays ,LCD Panel and switches ...Please guide me as to how i can connect my design to get these things working ...what data sheets to see ..what pin numbers to connect ....if there is a tutorial which explains all this ...it would be great ... > > Regards > Avinash |
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Re: FPGA DESIGN - Ed Corter - Apr 10 10:33:00 2004
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My name is Ed Corter I am very familiar with the verilog ----> Xilinx process and have advanced experience with digital design and virtex E chip usage.... feel free to email me with any questions you may have getting started. Please provide me with the inentity of the tools that you are using. PS the UCF file is the "user constraints file" - pin designation's for signal I\O - clock definition - timing constraint definition, timing group assignment (constaining of group timing) etc this info is used in the Place in Route of the Translated and Mapped design Ed --------------------------------- |
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