Sign in
Search fpga-cpu
Subscribe to fpga-cpu
fpga-cpu by Keywords
Altera | CISCifying | IDE | ISA | Java | JHDL | JTAG | LBU | MicroBlaze | PAR | PCI | RISC | SoC | Spartan | Transputers | Verilog | VHDL | Virtex | VLIW | WebPack | Xilinx | Xsoc | YARD-1A
Ads
Discussion Groups
See Also
Discussion Groups | FPGA-CPU | "The Knowledge": Virtex circuit tricks for add/mux
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
"The Knowledge": Virtex circuit tricks for add/mux - Jan Gray - Nov 12 18:09:00 2000
|
Many datapath circuits consist of an adder followed by a mux. For example, one appears in the PC/adder unit of xr16 -- next PC is either PC + PC-increment or is the jump effective address. This morning I figured out how to implement this add/mux circuit efficiently, one LUT per bit, for Virtex family architectures. See http://www.fpgacpu.org/index.html#001112 for more detail. Jan Gray Gray Research LLC |
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )