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Discussion Groups | FPGA-CPU | Dose Altera Nios support hardware-based multi-thread and how?
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Dose Altera Nios support hardware-based multi-thread and how? - qfmyue - Dec 2 1:45:00 2003
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In Altera development kits ,I can't find the description about it. The Nios(tm) CPU soft core is a 16/32-bit RISC CPU core,specially, it has the sliding register file windows technology. So I think it maybe support hardware multi-thread technology,but I can't find the relatial manual or reference. Dose Altera Nios support hardware-based multi-thread and how?? |
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Re: Dose Altera Nios support hardware-based multi-thread and how? - Martin Schoeberl - Apr 10 6:41:00 2004
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> In Altera development kits ,I can't find the description about it. > The Nios(tm) CPU soft core is a 16/32-bit RISC CPU core,specially, > it has the sliding register file windows technology. So I think it > maybe support hardware multi-thread technology,but I can't find the > relatial manual or reference. > Dose Altera Nios support hardware-based multi-thread and how?? No, there is no hardware support for multi-threading. Not more than a traditional timer interrupt. The sliding register window is used for faster function call and return. Martin ---------------------------------------------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/ |
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