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Discussion Groups | FPGA-CPU | How can I solve the problem"unsupported feature error" in VHDL for FPGA verify?
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
How can I solve the problem"unsupported feature error" in VHDL for FPGA verify? - ¨q¥J - Apr 10 8:41:00 2004
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Dear everybody: I had written a I2C slave interface for the requirement of my research and had compiled and simulated successfully in Modelsim. So I went to compile and dump it to the FPGA further. But when I did this using the MAXPLUSII 10.2,an error was happened and the error message was "unsupported feature error:signal parameter in a subprogram is not supported ". But I didn't understand what's wrong ,so I tried to test again to use the QUARTUS II 4.0 and found the error message was listed as below : Info: ******************************************************************* Info: Running Quartus II Analysis & Synthesis Info: Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Web Edition Info: Processing started: Sat Apr 10 19:07:10 2004 Info: Command: quartus_map --import_settings_files=on -- export_settings_files=off why_error -c why_error Info: Found 2 design units and 1 entities in source file why_error.vhd Info: Found design unit 1: why_error Info: Found entity 1: why_error Error: VHDL error at why_error.vhd(26): can't infer register for signal STATUS because signal does not hold its value outside clock edge Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings Error: Processing ended: Sat Apr 10 19:07:12 2004 Error: Elapsed time: 00:00:01 Error: Quartus II Full Compilation was unsuccessful. 1 error, 0 warnings ********************************************************************** and my source code is.. ---------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity why_error is port ( SDA: inout std_logic; SCL: in std_logic; RST: in std_logic; R_D_M: out std_logic ); end why_error; architecture understand of why_error is signal STATUS: std_logic; signal ADR_DIR_CHK: std_logic; begin process (RST,SDA,SCL) begin if RST='1' then SDA<='Z'; STATUS<='0'; R_D_M<='0'; ADR_DIR_CHK<='0'; elsif falling_edge(SDA) and SCL='1' then STATUS<='1'; elsif rising_edge(SDA) and SCL='1' then STATUS<='0'; ADR_DIR_CHK<='0'; R_D_M<='0'; end if; end process; end understand; ---------------------------------------------------------------------- From the error,I found the error was happened in the "line 26" of source code and that was the line "if RST='1' then...". I guessed that the cause of error was that the "STATUS" was only evented when the clock edge(SDA) was evented(Falling edge or Rising edge). That means when the "STATUS" was evented and pulled the signal up to "HIGH" at SDA(Falling edge ),It seemed "not" to be maintained the "HIGH" status till the situation that the clock edge(SDA) was evented again(Rising edge) and the "STATUS" would be pulled down to "LOW". But I hoped to maintain the STATUS signal till the SDA was evented, and it had been already simulated successfuly in the MODELSIM 5.4 using the source code above-mentioned. But it was "nonsuccessful" in "compile" and "synthesis" in the "MAXPLUSII" and "QUARTUS II". So.... How can I fix it to achieve my need and also satisfy the restriction of the "MAXPLUSII" and "QUARTUS II" that can be compiled successfully and dumped to the FPGA emulation board? If anybody know that please tell me~~~ Appreciate very much and Best regard. T.T.Gong |
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Re: How can I solve the problem"unsupported feature error" in VHDL for FPGA verify? - Shashikant Joshi - Apr 12 1:38:00 2004
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Hi, I think there is an error in the process. It is not correct to use elsif for a clock edge event. In your code the error is the last elsif statement. you can try the following modifications ... library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity why_error is port ( SDA: inout std_logic; SCL: in std_logic; RST: in std_logic; R_D_M: out std_logic ); end why_error; architecture understand of why_error is signal STATUS: std_logic; signal ADR_DIR_CHK: std_logic; begin p1 : process (RST,SDA,SCL) begin if RST='1' then STATUS<='0'; elsif SCL='1' then STATUS<= not SDA; end if; end process; p2 : process (RST,SDA,SCL) begin if RST='1' then SDA<='Z'; R_D_M<='0'; ADR_DIR_CHK<='0'; elsif rising_edge(SDA) then if SCL = '1' then ADR_DIR_CHK<='0'; R_D_M<='0'; end if; end if; end process; end understand; Regards Shashikant email : --- ¨q¥J <> wrote: > Dear everybody: > > I had written a I2C slave interface for the > requirement of my > research and had compiled and simulated successfully > in Modelsim. > So I went to compile and dump it to the FPGA > further. > But when I did this using the MAXPLUSII 10.2,an > error was happened and > the error message was "unsupported feature > error:signal parameter in > a subprogram is not supported ". > But I didn't understand what's wrong ,so I tried to > test again to use > the QUARTUS II 4.0 and found the error message was > listed as below : > > Info: > ******************************************************************* > > Info: Running Quartus II Analysis & Synthesis > Info: Version 4.0 Build 214 3/25/2004 Service Pack > 1 SJ Web Edition > Info: Processing started: Sat Apr 10 19:07:10 2004 > Info: Command: quartus_map > --import_settings_files=on -- > export_settings_files=off why_error -c why_error > Info: Found 2 design units and 1 entities in source > file > why_error.vhd > Info: Found design unit 1: why_error > Info: Found entity 1: why_error > Error: VHDL error at why_error.vhd(26): can't infer > register for > signal > STATUS because signal does not hold its value > outside clock edge > Error: Quartus II Analysis & Synthesis was > unsuccessful. 1 error, 0 > warnings > Error: Processing ended: Sat Apr 10 19:07:12 2004 > Error: Elapsed time: 00:00:01 > Error: Quartus II Full Compilation was unsuccessful. > 1 error, 0 > warnings > ********************************************************************** > and my source code is.. > ---------------------------------------------------------------------- > > library ieee; > use ieee.std_logic_1164.all; > use ieee.std_logic_arith.all; > use ieee.std_logic_unsigned.all; > > entity why_error is port ( > SDA: inout std_logic; > SCL: in std_logic; > RST: in std_logic; > R_D_M: out std_logic > ); > end why_error; > > architecture understand of why_error is > > signal STATUS: std_logic; > signal ADR_DIR_CHK: std_logic; > > begin > > process (RST,SDA,SCL) > begin > > if RST='1' then > SDA<='Z'; > STATUS<='0'; > R_D_M<='0'; > ADR_DIR_CHK<='0'; > > elsif falling_edge(SDA) and SCL='1' then > STATUS<='1'; > > elsif rising_edge(SDA) and SCL='1' then > STATUS<='0'; > ADR_DIR_CHK<='0'; > R_D_M<='0'; > > end if; > end process; > > end understand; > ---------------------------------------------------------------------- > > From the error,I found the error was happened in the > "line 26" of > source code and that was the line "if RST='1' > then...". > I guessed that the cause of error was that the > "STATUS" was only > evented when the clock edge(SDA) was evented(Falling > edge or Rising > edge). > That means when the "STATUS" was evented and pulled > the signal up > to "HIGH" at SDA(Falling edge ),It seemed "not" to > be maintained > the "HIGH" status till the situation that the clock > edge(SDA) was > evented again(Rising edge) and the "STATUS" would be > pulled down > to "LOW". > But I hoped to maintain the STATUS signal till the > SDA was evented, > and it had been already simulated successfuly in the > MODELSIM 5.4 > using the source code above-mentioned. But it was > "nonsuccessful" > in "compile" and "synthesis" in the "MAXPLUSII" and > "QUARTUS II". > So.... > How can I fix it to achieve my need and also satisfy > the restriction > of the "MAXPLUSII" and "QUARTUS II" that can be > compiled > successfully and dumped to the FPGA emulation board? > If anybody know that please tell me~~~ > > Appreciate very much and Best regard. > > T.T.Gong > > > To post a message, send it to: > > To unsubscribe, send a blank message to: > > Yahoo! Groups Links __________________________________ |
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AW: How can I solve the problem"unsupported feature error" in VHDL for FPGA verify? - Thomas Sedlaczek - Apr 12 11:58:00 2004
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Hi T.T.Gong, I have just looked at your source and I am wondering about a few things. First you try to design a latch with asynchronous reset and which will latch on the rising as well as on the falling edge of your data input. That is at least very unconventional! :-) Why you do not use the serial clock SCL to come to a synchronous design? The other thing is that you have defined a reset state for any signal but only for some you have defined the ifelse state. What is happened to these signals?? You have to define this or if they are never changing there state within your process then throw them away. Especially for your problem, there is a very nice I2C core in VHDL on the Opercores project page. It is written by Richard Herveille in a nice style, maybe you should to have a look at it and try to understand who the core works and to adapt a bit of the coding style. Look here: http://www.opencores.org/projects.cgi/web/i2c/overview Good luck with your project! Regards Thomas _______________________________________________ Thomas Sedlaczek Mecklenburger Str. 27 38440 Wolfsburg Germany Tel: +49 (0)5361-898825 Lab: +49 (0)5361-831910 Mobile: +49 (0)175-4015118 Email: _______________________________________________ -----Ursprüngliche Nachricht----- Von: . com [mailto: s.yahoo.com] Im Auftrag von ¨q¥J Gesendet: 10 April 2004 15:41 An: Betreff: [fpga-cpu] How can I solve the problem"unsupported feature error" in VHDL for FPGA verify? Dear everybody: I had written a I2C slave interface for the requirement of my research and had compiled and simulated successfully in Modelsim. So I went to compile and dump it to the FPGA further. But when I did this using the MAXPLUSII 10.2,an error was happened and the error message was "unsupported feature error:signal parameter in a subprogram is not supported ". But I didn't understand what's wrong ,so I tried to test again to use the QUARTUS II 4.0 and found the error message was listed as below : Info: ******************************************************************* Info: Running Quartus II Analysis & Synthesis Info: Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Web Edition Info: Processing started: Sat Apr 10 19:07:10 2004 Info: Command: quartus_map --import_settings_files=on -- export_settings_files=off why_error -c why_error Info: Found 2 design units and 1 entities in source file why_error.vhd Info: Found design unit 1: why_error Info: Found entity 1: why_error Error: VHDL error at why_error.vhd(26): can't infer register for signal STATUS because signal does not hold its value outside clock edge Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings Error: Processing ended: Sat Apr 10 19:07:12 2004 Error: Elapsed time: 00:00:01 Error: Quartus II Full Compilation was unsuccessful. 1 error, 0 warnings ********************************************************************** and my source code is.. ---------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity why_error is port ( SDA: inout std_logic; SCL: in std_logic; RST: in std_logic; R_D_M: out std_logic ); end why_error; architecture understand of why_error is signal STATUS: std_logic; signal ADR_DIR_CHK: std_logic; begin process (RST,SDA,SCL) begin if RST='1' then SDA<='Z'; STATUS<='0'; R_D_M<='0'; ADR_DIR_CHK<='0'; elsif falling_edge(SDA) and SCL='1' then STATUS<='1'; elsif rising_edge(SDA) and SCL='1' then STATUS<='0'; ADR_DIR_CHK<='0'; R_D_M<='0'; end if; end process; end understand; ---------------------------------------------------------------------- From the error,I found the error was happened in the "line 26" of source code and that was the line "if RST='1' then...". I guessed that the cause of error was that the "STATUS" was only evented when the clock edge(SDA) was evented(Falling edge or Rising edge). That means when the "STATUS" was evented and pulled the signal up to "HIGH" at SDA(Falling edge ),It seemed "not" to be maintained the "HIGH" status till the situation that the clock edge(SDA) was evented again(Rising edge) and the "STATUS" would be pulled down to "LOW". But I hoped to maintain the STATUS signal till the SDA was evented, and it had been already simulated successfuly in the MODELSIM 5.4 using the source code above-mentioned. But it was "nonsuccessful" in "compile" and "synthesis" in the "MAXPLUSII" and "QUARTUS II". So.... How can I fix it to achieve my need and also satisfy the restriction of the "MAXPLUSII" and "QUARTUS II" that can be compiled successfully and dumped to the FPGA emulation board? If anybody know that please tell me~~~ Appreciate very much and Best regard. T.T.Gong To post a message, send it to: To unsubscribe, send a blank message to: Yahoo! Groups Links |
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Re: How can I solve the problem"unsupported feature error" in VHDL for FPGA verify? - Bairros - Jun 12 11:42:00 2004
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Hello everybody !!1 Excuse me, my interruption I am Electrical Engineering student from Brazil and I need to know where can I get some samples about PLD´s parts ??? ----- Original Message ----- From: "Shashikant Joshi" <> To: <> Cc: <> Sent: Monday, April 12, 2004 3:38 AM Subject: Re: [fpga-cpu] How can I solve the problem"unsupported feature error" in VHDL for FPGA verify? Hi, I think there is an error in the process. It is not correct to use elsif for a clock edge event. In your code the error is the last elsif statement. you can try the following modifications ... library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity why_error is port ( SDA: inout std_logic; SCL: in std_logic; RST: in std_logic; R_D_M: out std_logic ); end why_error; architecture understand of why_error is signal STATUS: std_logic; signal ADR_DIR_CHK: std_logic; begin p1 : process (RST,SDA,SCL) begin if RST='1' then STATUS<='0'; elsif SCL='1' then STATUS<= not SDA; end if; end process; p2 : process (RST,SDA,SCL) begin if RST='1' then SDA<='Z'; R_D_M<='0'; ADR_DIR_CHK<='0'; elsif rising_edge(SDA) then if SCL = '1' then ADR_DIR_CHK<='0'; R_D_M<='0'; end if; end if; end process; end understand; Regards Shashikant email : --- ¨q¥J <> wrote: > Dear everybody: > > I had written a I2C slave interface for the > requirement of my > research and had compiled and simulated successfully > in Modelsim. > So I went to compile and dump it to the FPGA > further. > But when I did this using the MAXPLUSII 10.2,an > error was happened and > the error message was "unsupported feature > error:signal parameter in > a subprogram is not supported ". > But I didn't understand what's wrong ,so I tried to > test again to use > the QUARTUS II 4.0 and found the error message was > listed as below : > > Info: > ******************************************************************* > > Info: Running Quartus II Analysis & Synthesis > Info: Version 4.0 Build 214 3/25/2004 Service Pack > 1 SJ Web Edition > Info: Processing started: Sat Apr 10 19:07:10 2004 > Info: Command: quartus_map > --import_settings_files=on -- > export_settings_files=off why_error -c why_error > Info: Found 2 design units and 1 entities in source > file > why_error.vhd > Info: Found design unit 1: why_error > Info: Found entity 1: why_error > Error: VHDL error at why_error.vhd(26): can't infer > register for > signal > STATUS because signal does not hold its value > outside clock edge > Error: Quartus II Analysis & Synthesis was > unsuccessful. 1 error, 0 > warnings > Error: Processing ended: Sat Apr 10 19:07:12 2004 > Error: Elapsed time: 00:00:01 > Error: Quartus II Full Compilation was unsuccessful. > 1 error, 0 > warnings > ********************************************************************** > and my source code is.. > ---------------------------------------------------------------------- > > library ieee; > use ieee.std_logic_1164.all; > use ieee.std_logic_arith.all; > use ieee.std_logic_unsigned.all; > > entity why_error is port ( > SDA: inout std_logic; > SCL: in std_logic; > RST: in std_logic; > R_D_M: out std_logic > ); > end why_error; > > architecture understand of why_error is > > signal STATUS: std_logic; > signal ADR_DIR_CHK: std_logic; > > begin > > process (RST,SDA,SCL) > begin > > if RST='1' then > SDA<='Z'; > STATUS<='0'; > R_D_M<='0'; > ADR_DIR_CHK<='0'; > > elsif falling_edge(SDA) and SCL='1' then > STATUS<='1'; > > elsif rising_edge(SDA) and SCL='1' then > STATUS<='0'; > ADR_DIR_CHK<='0'; > R_D_M<='0'; > > end if; > end process; > > end understand; > ---------------------------------------------------------------------- > > From the error,I found the error was happened in the > "line 26" of > source code and that was the line "if RST='1' > then...". > I guessed that the cause of error was that the > "STATUS" was only > evented when the clock edge(SDA) was evented(Falling > edge or Rising > edge). > That means when the "STATUS" was evented and pulled > the signal up > to "HIGH" at SDA(Falling edge ),It seemed "not" to > be maintained > the "HIGH" status till the situation that the clock > edge(SDA) was > evented again(Rising edge) and the "STATUS" would be > pulled down > to "LOW". > But I hoped to maintain the STATUS signal till the > SDA was evented, > and it had been already simulated successfuly in the > MODELSIM 5.4 > using the source code above-mentioned. But it was > "nonsuccessful" > in "compile" and "synthesis" in the "MAXPLUSII" and > "QUARTUS II". > So.... > How can I fix it to achieve my need and also satisfy > the restriction > of the "MAXPLUSII" and "QUARTUS II" that can be > compiled > successfully and dumped to the FPGA emulation board? > If anybody know that please tell me~~~ > > Appreciate very much and Best regard. > > T.T.Gong > > > To post a message, send it to: > > To unsubscribe, send a blank message to: > > Yahoo! Groups Links __________________________________ To post a message, send it to: To unsubscribe, send a blank message to: Yahoo! Groups Links |
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Re: How can I solve the problem"unsupported feature error" in VHDL for FPGA verify? - eka antonius - Jul 12 23:03:00 2004
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1.) if rising_edge(SDA) then R_D_M <= '0'; end if; mean: the value of 'R_D_M' is update only very 'rising edge' and the value constant every HIGH and LOW signal of SDA. 2.) if rising_edge(SDA) then STATUS <= '0'; elsif falling_edge(SDA) then STATUS <= '1'; end if; mean: the value of 'STATUS' is update every 'rising edge' or HIGH signal and every 'falling_edge' or LOW signal of SDA. May be not all of the compiler can recognize this situation, so change it to: if SDA = '1' then -- SDA HIGH STATUS <= '0'; elsif SDA = '0' then -- SDA LOW STATUS <= '1'; end if; > ----- Original Message ----- > From: "Shashikant Joshi" <> > To: <> > Cc: <> > Sent: Monday, April 12, 2004 3:38 AM > Subject: Re: [fpga-cpu] How can I solve the > problem"unsupported feature > error" in VHDL for FPGA verify? > Hi, > > I think there is an error in the process. > > It is not correct to use elsif for a clock edge > event. > In your code the error is the last elsif statement. > > you can try the following modifications ... > > library ieee; > use ieee.std_logic_1164.all; > use ieee.std_logic_arith.all; > use ieee.std_logic_unsigned.all; > > entity why_error is port ( > SDA: inout std_logic; > SCL: in std_logic; > RST: in std_logic; > R_D_M: out std_logic > ); > end why_error; > > architecture understand of why_error is > > signal STATUS: std_logic; > signal ADR_DIR_CHK: std_logic; > > begin > > p1 : process (RST,SDA,SCL) > begin > if RST='1' then > STATUS<='0'; > elsif SCL='1' then > STATUS<= not SDA; > end if; > end process; > > p2 : process (RST,SDA,SCL) > begin > if RST='1' then > SDA<='Z'; > R_D_M<='0'; > ADR_DIR_CHK<='0'; > elsif rising_edge(SDA) then > if SCL = '1' then > ADR_DIR_CHK<='0'; > R_D_M<='0'; > end if; > end if; > end process; > > end understand; > > > Regards > Shashikant > email : > --- ¨q¥J <> wrote: > > Dear everybody: > > > > I had written a I2C slave interface for the > > requirement of my > > research and had compiled and simulated > successfully > > in Modelsim. > > So I went to compile and dump it to the FPGA > > further. > > But when I did this using the MAXPLUSII 10.2,an > > error was happened and > > the error message was "unsupported feature > > error:signal parameter in > > a subprogram is not supported ". > > But I didn't understand what's wrong ,so I tried > to > > test again to use > > the QUARTUS II 4.0 and found the error message was > > listed as below : > > > > Info: > > > ******************************************************************* > > > > Info: Running Quartus II Analysis & Synthesis > > Info: Version 4.0 Build 214 3/25/2004 Service > Pack > > 1 SJ Web Edition > > Info: Processing started: Sat Apr 10 19:07:10 > 2004 > > Info: Command: quartus_map > > --import_settings_files=on -- > > export_settings_files=off why_error -c why_error > > Info: Found 2 design units and 1 entities in > source > > file > > why_error.vhd > > Info: Found design unit 1: why_error > > Info: Found entity 1: why_error > > Error: VHDL error at why_error.vhd(26): can't > infer > > register for > > signal > > STATUS because signal does not hold its value > > outside clock edge > > Error: Quartus II Analysis & Synthesis was > > unsuccessful. 1 error, 0 > > warnings > > Error: Processing ended: Sat Apr 10 19:07:12 2004 > > Error: Elapsed time: 00:00:01 > > Error: Quartus II Full Compilation was > unsuccessful. > > 1 error, 0 > > warnings > > > ********************************************************************** > > > > > > and my source code is.. > > > ---------------------------------------------------------------------- > > > > library ieee; > > use ieee.std_logic_1164.all; > > use ieee.std_logic_arith.all; > > use ieee.std_logic_unsigned.all; > > > > entity why_error is port ( > > SDA: inout std_logic; > > SCL: in std_logic; > > RST: in std_logic; > > R_D_M: out std_logic > > ); > > end why_error; > > > > architecture understand of why_error is > > > > signal STATUS: std_logic; > > signal ADR_DIR_CHK: std_logic; > > > > begin > > > > process (RST,SDA,SCL) > > begin > > > > if RST='1' then > > SDA<='Z'; > > STATUS<='0'; > > R_D_M<='0'; > > ADR_DIR_CHK<='0'; > > > > elsif falling_edge(SDA) and SCL='1' then > > STATUS<='1'; > > > > elsif rising_edge(SDA) and SCL='1' then > > STATUS<='0'; > > ADR_DIR_CHK<='0'; > > R_D_M<='0'; > > > > end if; > > end process; > > > > end understand; > > > ---------------------------------------------------------------------- > > > > From the error,I found the error was happened in > the > > "line 26" of > > source code and that was the line "if RST='1' > > then...". > > I guessed that the cause of error was that the > > "STATUS" was only > > evented when the clock edge(SDA) was > evented(Falling > > edge or Rising > > edge). > > That means when the "STATUS" was evented and > pulled > > the signal up > > to "HIGH" at SDA(Falling edge ),It seemed "not" to > === message truncated === __________________________________ |
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