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This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
YARD-1A and WebPack XST - Brian Davis - Nov 12 23:42:00 2000
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XST first impressions: I've spent a few nights with the latest Xilinx WebPack, the YARD-1A VHDL source, and my trusty code machete; last night, a "blink the LED's" program booted on an XC2S100 (YARD-1A core, 2 Kbyte block RAM, I/O ports) synthesized entirely with the Webpack XST :-) The required code changes weren't as severe as I'd anticipated from reading the 3.1i XST manual; although XST's VHDL language support is kinda lame in some areas, it turned out to be better than that documented in the manual. Most of the items I ran into were more of an annoyance than a show-stopper limitation; in the event that anyone else is code-wrestling with XST, here's a quick summary of what I needed to change in my code: - translate_on/off syntax "-- synopsys translate_xxx" works "-- synthesis translate_xxx" ignored - chokes on aliases in process sensitivity list - chokes on sliced aliases in expressions - doesn't allow "begin" in an "if .. generate" ( VHDL-87 syntax rules ) - doesn't allow string concatenation for long attribute lines - reg. file and stack memories needed slight recoding to infer CLB RAM's instead of registers I'd also recommend doing a search on "XST" in the Xilinx answers database for more issues like those above. YARD-1A with block RAM: I'm running the core with 4 block RAM's in dual port mode, using one RAM port as a 1K x 16 instruction memory, and the other as a 512 x 32 data RAM with byte write enables. I haven't modified the processor to stall on memory accesses yet, so I'm doing single cycle loads with the registered block RAM by flipping the clock sense on the data memory port. As the memory EA generation is on the critical path, this slows down the 32 bit core to ~30 MHz until I implement multi-cycle loads. Brian Davis |
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Re: YARD-1A and WebPack XST - Author Unknown - Nov 13 2:26:00 2000
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> XST first impressions: > > I've spent a few nights with the latest Xilinx WebPack, > the YARD-1A VHDL source, and my trusty code machete; last > night, a "blink the LED's" program booted on an XC2S100 > (YARD-1A core, 2 Kbyte block RAM, I/O ports) synthesized > entirely with the Webpack XST :-) Just so everyone is aware, Xilinx Student Edition 2.1i ($55 from www.xess.com) can target up to Virtex-50/50E, and Spartan2-150 parts (not Spartan2-200.) This would give you the option of using FPGA Express, for relatively a low price, if XST proves to have some show-stoppers. I've found that XSE2.1i allows targeteting devices up to the XCV-1000/1000E, which is nice. The synthesis constraint editor is still disabled (as it was with XSE 1.5). Except for the constraint editor, I can't find any operative difference between XSE 2.1i and the commercial Foundation Express 2.1i I've used at work. |
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