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Discussion Groups | FPGA-CPU | [ANN] Altera Cyclone EP1C12 FPGA Board
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
[ANN] Altera Cyclone EP1C12 FPGA Board - Martin Schoeberl - May 4 2:30:00 2004
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The successful Cyclone EP1C6 FPGA module is now available with the larger Cyclon EP1C12. The board is an ideal module for SoC design with soft-core CPUs such as NIOS or JOP. Additional to the FPGA it conatins a three stage memory hirarchy: Fast asynchron memory as main memory. Conventional Flash for coniguration data and application. A big NAND Flash for solide state disc. The board comes as module ready to be plugged in your expansion board or an an expansion board with Ethernet connection. The board is not only usefull for FPGA prototyping, but is a ready to use module for your application board. Ask for price on larger quantities. The Facts: Altera Cyclone EP1C6Q240 or EP1C12Q240 FPGA Step down voltage regulator (1V5) Crystal clock (20 MHz) at the PLL input (up to 640 MHz) 512KB Flash (for FPGA configuration and program) up to 1MB fast async Ram up to 128MB NAND Flash ByteBlasterMV port Watchdog with LED EPM7064 PLD to configure Cyclone from flash (on watchdog reset) serial interface (MAX3232) 56 general IO pins The RAM consists of two independent 16 Bit banks (with own address and control lines). Both RAM chips are on the back side of the PCB direct under the FPGA pins. The traces are very short (below 10 mm) so it is possible to use the RAMs at full speed without reflection problems. The two banks can be combined to form 32 Bit RAM or support two independent CPU cores (A dual processor system in a FPGA :-). Further information: http://www.jopdesign.com/cyclone/index.jsp Kind regards Martin Schoeberl |
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