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Discussion Groups | FPGA-CPU | I want to join any RISC processor design in Verilog HDL.
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
I want to join any RISC processor design in Verilog HDL. - Ben A. Abderazek - May 14 5:20:00 2004
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Hello, Is there is any open CPU design project that I can join as a volunteer.? I can help designing a part of an open RISC processor in Verilog HDL. Regards, /Ben UEC, IS. [Non-text portions of this message have been removed] |
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Re: I want to join any RISC processor design in Verilog HDL. - Tomasz Sztejka - May 19 1:58:00 2004
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--- " Ben A. Abderazek" <> wrote: > Hello, > Is there is any open CPU design project that I can join as a > volunteer.? (...) Check the : http://www.opencores.org, some projects may need help. Tomasz Sztejka. ____________________________________________________________ Yahoo! Messenger - Communicate instantly..."Ping" your friends today! Download Messenger Now http://uk.messenger.yahoo.com/download/index.html |
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