Sign in
Search fpga-cpu
Subscribe to fpga-cpu
fpga-cpu by Keywords
Altera | CISCifying | IDE | ISA | Java | JHDL | JTAG | LBU | MicroBlaze | PAR | PCI | RISC | SoC | Spartan | Transputers | Verilog | VHDL | Virtex | VLIW | WebPack | Xilinx | Xsoc | YARD-1A
Ads
Discussion Groups
Discussion Groups | FPGA-CPU | Re: Question about the STACK size: + Instruction Register
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Re: Question about the STACK size: + Instruction Register - Ben A. Abderazek - May 23 20:04:00 2004
|
Thank you Towas for the details. I understand it very well and I implement a hardware stack as a first implementation. I do not have so much experience in processor and verilog HDL design that is why I am asking probably very basic question for you. I have another question about the size of the instruction register. I want to fetch four instruction per cycle from the main memory. So, I am thinking to implement 4 instruction-registers (ir) in hardware (one for each instruction). My question is: first is it possible to fetch 4 instructions per memory read cycle? Second, can I just use one "ir" for the four instructions which I fetched from the memory? I assume that one instruction is fetched during 1/4 of a cycle. The module I wrote in Verilog HDl for the fetch unit is: ======================================== module inst_fetch ( Ins_add_in0, Ins_add_in1, Ins_add_in2, Ins_add_in3, // Ins_code_in0, Ins_code_in1, Ins_code_in2, Ins_code_in3, // Ins_add_out0, Ins_add_out1, Ins_add_out2, Ins_add_out3, // Ins_code_out0, Ins_code_out1, Ins_code_out2, Ins_code_out3, // clk, // system clock PC, // program counter sf // suspend flag ); ======================================= Pelase note that all instructions are two bide wide. I want to know whether this is a practical implmentation or not. If what I said that this is not practical, then how other processors fetch or execute multiinstructions per cycle ? Many thaks for your help, /Ben |
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )