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Discussion Groups | FPGA-CPU | xr16 interrupts

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

xr16 interrupts - Rob Finch - May 25 23:06:00 2004

I've been scratching my head about this tonight:

The xr16 waits until it can place an interrupt instruction outside of
the branch shadow, before putting an interrupt instruction in the
instruction stream.

I'm wondering if interrupts could be made to work by making a
hardware interrupt a non-nullable instruction, then placing it in the
instruction stream as soon as it occurs (excepting immediates and
other decoder interrupt inhibits), rather than waiting until there is
a spot outside of a branch / jump shadow. I think it's only a matter
of checking the dc_int and if_int signals during annul checking.

Would the interrupt work then, even if it was in the branch shadow ?
It looks to me like the correct return address would still be saved
off. Has anyone rebuilt the xsoc system in a Spartan2/2e system ? Do you
have some sort of boot-strap loader available that will fit into
block ram ?

Rob



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