Sign in
Search fpga-cpu
Subscribe to fpga-cpu
fpga-cpu by Keywords
Altera | CISCifying | IDE | ISA | Java | JHDL | JTAG | LBU | MicroBlaze | PAR | PCI | RISC | SoC | Spartan | Transputers | Verilog | VHDL | Virtex | VLIW | WebPack | Xilinx | Xsoc | YARD-1A
Ads
Discussion Groups
Discussion Groups | FPGA-CPU | Re: Re: Xilinx Web Pack - latest version
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Re: Re: Xilinx Web Pack - latest version - Arius - Rick Collins - Aug 19 14:48:00 2004
|
At 03:26 PM 8/19/2004, you wrote: >I moved the process block to follow all the combinatorial logic and >precede the external entity instances and things got better. In the >original source the process was in the middle of the combinatorial >logic statements. > >Reasonable result? I would say no. The relative location of code in the concurrent statement region has no effect on the execution or the meaning of the code. One problem with trying to help you is that you don't describe the nature of the problem. You use phrases like "things got better", "the emulation no longer functions properly" and "the emulation blows up". If your emulation is blowing up, you need to consult a demolitions expert. ;) Can you explain what does and does not work when you change the lines of code? Obviously "getting better" is not the same as working. Rick Collins Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX |
|
|
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: Xilinx Web Pack - latest version - rtstofer - Aug 28 2:09:00 2004
|
I pulled the original post after I found MY error. I had left an input signal unconnected and not pulled up. Sometimes the system would work, sometimes not. It wasn't related to code location at all. I would never have done that with discrete components, I wonder why it didn't occur to me sooner. In any event, CP/M 2.2 is now running with an old Seagate hard disk and things are looking up. I guess the next step is to kick up the clock and see how fast this thing will run. 20 or 30 MHz would be impressive! The only issue should be wait states for off-chip I/O and that may not be terribly difficult to implement. Thanks for the replies! Implementing this project has been a terrific learing experience. No point in starting with the flashing light tutorials... --- In , Arius - Rick Collins <dsprelated@a...> wrote: > At 03:26 PM 8/19/2004, you wrote: > > >I moved the process block to follow all the combinatorial logic and > >precede the external entity instances and things got better. In the > >original source the process was in the middle of the combinatorial > >logic statements. > > > >Reasonable result? > I would say no. The relative location of code in the concurrent statement > region has no effect on the execution or the meaning of the code. > > One problem with trying to help you is that you don't describe the nature > of the problem. You use phrases like "things got better", "the emulation > no longer functions properly" and "the emulation blows up". If your > emulation is blowing up, you need to consult a demolitions expert. ;) > > Can you explain what does and does not work when you change the lines of > code? Obviously "getting better" is not the same as working. > > > Rick Collins > > rick.collins@a... > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX |
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )