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Discussion Groups | FPGA-CPU | Re: Xilinx Web Pack - latest version

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

Re: Xilinx Web Pack - latest version - Nigel Lee - Aug 23 0:12:00 2004

It may depend on the synthesizer, you can probably identify the problem
by checking the corresponding synthesized circuit.
If you simply want to avoid the problem, I would suggest handling the
signals in separate processes?
i.e.:
Reset_s_p: process(Reset_n, Clk)
..begin
....if Reset_n = '0' then
......Reset_s <= '0';
....elsif Clk'event and Clk = '1' then
......Reset_s <= '1';
....end if;
..end process; -- process for Reset_s

Mirror_p: process(Reset_n, Clk)
..begin
....if Reset_n = '0' then
......Mirror <= '0';
....elsif Clk'event and Clk = '1' then
......if IOWR_n = '0' and A(7 downto 0) = "11110000" then -- <======
........Mirror <= D(0);
......end if;
....end if;
end process; -- process for Mirror

FlashCount_p: process (Reset_n, Clk)
..begin
....if Reset_n = '0' then
......FlashCount <= (others => '0');
....elsif Clk'event and Clk = '1' then
......FlashCount <= FlashCount + 1;
....end if;
end process; -- process for FlashCount

Good luck!

Regards,
Nigel

-----Original Message-----
From: [mailto:]
Message: 2
Date: Thu, 19 Aug 2004 19:26:36 -0000
From: "rtstofer" <>
Subject: Re: Xilinx Web Pack - latest version I moved the process block to follow all the combinatorial logic and
precede the external entity instances and things got better. In the
original source the process was in the middle of the combinatorial
logic statements.

Reasonable result? --- In , "rtstofer" <rstofer@p...> wrote:
> I have been working on the T80 core and BurchEd development
board.
> The problem is that whenever I make certain types of changes to
the
> upper level VHDL the emulation blows up. For example if I change
> just one line in the following:
>
> process (Reset_n, Clk)
> ..begin
> ....if Reset_n = '0' then
> ......Reset_s <= '0';
> ......Mirror <= '0';
> ......FlashCount <= (others => '0');
> ....elsif Clk'event and Clk = '1' then
> ......Reset_s <= '1';
> ......if IOWR_n = '0' and A(7 downto 4) = "1111" then
> ........Mirror <= D(0);
> ......end if;
> ......FlashCount <= FlashCount + 1;
> ....end if;
> end process;
>
> to :
>
> process (Reset_n, Clk)
> ..begin
> ....if Reset_n = '0' then
> ......Reset_s <= '0';
> ......Mirror <= '0';
> ......FlashCount <= (others => '0');
> ....elsif Clk'event and Clk = '1' then
> ......Reset_s <= '1';
> ......if IOWR_n = '0' and A(7 downto 0) = "11110000" then --
<======
> ........Mirror <= D(0);
> ......end if;
> ......FlashCount <= FlashCount + 1;
> ....end if;
> end process;
>
> the emulation no longer functions properly yet the only change was
> to fully specify an I/O address. There are other examples (for
> example just adding a signal: debug_sig <= Mirror;) where making a
> seemingly small change causes the entire thing to quit working.
>
> Any thoughts on this problem? It's almost certain that I am not
the
> first person to encounter this.
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