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Discussion Groups | FPGA-CPU | new paper on FPGA CPU and SoC design at www.fpgacpu.org
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
new paper on FPGA CPU and SoC design at www.fpgacpu.org - Jan Gray - Dec 1 21:23:00 2000
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Late in November I finished the design of new processor, the gr0040, and a new version of the XSOC system-on-a-chip framework, and retargeted a C compiler, assembler, and simulator to it. I wrote up the whole thing as a synthesizable literate Verilog program, which is my paper for DesignCon 2001. Abstract: "This paper presents the complete design of a simple FPGA RISC processor core and system-on-a-chip in synthesizable Verilog. It defines a RISC instruction set architecture and then describes how to implement every part of the processor. Next, an interrupt facility is added. The second half of the paper describes the design and implementation of the system-on-a-chip -- on-chip RAM, peripheral bus, and peripherals. Throughout, FPGA-specific issues and optimizations are cited. The paper concludes with a comparison with other FPGA processor cores and a brief discussion of software tools issues." Visit www.fpgacpu.org for a link to the paper. Comments appreciated. Jan Gray, Gray Research LLC |
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Re: new paper on FPGA CPU and SoC design at www.fpgacpu.org - Author Unknown - Dec 13 7:38:00 2000
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because I will design a SoPC, so I want to learn something from this paper, but I found there are so many abbreviations,some I couldn't guess ,that I couldn't understand it well. and I think it's helpful if there is a functional block diagram. ok,it's just my opinion. --- In , "Jan Gray" <jsgray@a...> wrote: > Late in November I finished the design of new processor, the gr0040, and a > new version of the XSOC system-on-a-chip framework, and retargeted a C > compiler, assembler, and simulator to it. I wrote up the whole thing as a > synthesizable literate Verilog program, which is my paper for DesignCon > 2001. > > Abstract: "This paper presents the complete design of a simple FPGA RISC > processor core and system-on-a-chip in synthesizable Verilog. It defines a > RISC instruction set architecture and then describes how to implement every > part of the processor. Next, an interrupt facility is added. The second half > of the paper describes the design and implementation of the > system-on-a-chip -- on-chip RAM, peripheral bus, and peripherals. > Throughout, FPGA-specific issues and optimizations are cited. The paper > concludes with a comparison with other FPGA processor cores and a brief > discussion of software tools issues." > > Visit www.fpgacpu.org for a link to the paper. Comments appreciated. > > Jan Gray, Gray Research LLC |
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RE: Re: new paper on FPGA CPU and SoC design at www.fpgacpu.org - Jan Gray - Jan 5 0:07:00 2001
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> From: [mailto:] > > because I will design a SoPC, > so I want to learn something from this paper, > but I found there are so many abbreviations,some I couldn't > guess ,that I couldn't understand it well. > and I think it's helpful if there is a functional block diagram. > ok,it's just my opinion. A belated thank you for your comments, they are useful and appreciated, and will help improve the next version of the paper (if there is one), or at any rate, future projects I do. [Unrelated note: last month I said I'd try to put out my Virtex changes for XSOC/xr16 soon. Alas, something else came up and delayed that work yet again. Sorry. Please stand by.] Jan Gray, Gray Research LLC |
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