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Discussion Groups | FPGA-CPU | ANN: Introducing MANIK - a 32 bit Soft-Core RISC Processor


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This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

ANN: Introducing MANIK - a 32 bit Soft-Core RISC Processor - sandeep94404 - Oct 15 12:13:00 2004



http://www.niktech.com

Hardware Features

ˇ Data Path Width 32 bits
ˇ Most instructions are 16 bit. PC Relative jump instructions
are 32 bit.
ˇ Four stage pipeline.
ˇ Von Neumann Architecture (Data and Instruction in the same
address space).
ˇ Sixteen, 32 bit General Purpose Registers.
ˇ Four USER defined instructions (with Register File Write
back capability).
ˇ Parallel execution of independent Load/Store, Multiply/Shift ,
User Defined Instructions and ALU instructions
(In order issue; Out of order completion)
ˇ Some Conditional Instructions (Reduces branches & increases
code density).
ˇ Built in 32 bit Timer.
ˇ Power Down Mode.
ˇ 32x32 Multiplier (Multi cycle execution).

Software Development Tools
ˇ GNU Assembler, Linker (binutils)
ˇ GCC (C Compiler)
ˇ GDB (Debugger) and Instruction Set Simulator
ˇ Standalone C-Library (RedHat newlib)
ˇ Modified version of DietLibc

Size and Performance.

Netlists for the current implementation is available for XILINX
Virtex,Spartan-II and Spartan-IIE; it utilizes 1375 LUTs (809
slices); the size includes a 32 bit timer and a 32x32 bit LUT
based multiplier.

The design has been tested to operate at 60MHZ on a Spartan-II
(speed grade -6).

Netlists, Documentation and Development tools can be downloaded
from http://www.niktech.com.





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RE: ANN: Introducing MANIK - a 32 bit Soft-Core RISC Processor - Perez Ramas, Javier Basilio - Dec 17 5:34:00 2004

I've take a look to your web but I can't find any information about licensing. What kind of license do you have? Is it a free processor?

Best regards,

  Javier Basilio Pérez Ramas > -----Mensaje original-----
> De: sandeep94404 [mailto:]
> Enviado el: viernes, 15 de octubre de 2004 19:14
> Para:
> Asunto: [fpga-cpu] ANN: Introducing MANIK - a 32 bit Soft-Core RISC
> Processor > http://www.niktech.com
>
> Hardware Features
>
> ˇ Data Path Width 32 bits
> ˇ Most instructions are 16 bit. PC Relative jump instructions
> are 32 bit.
> ˇ Four stage pipeline.
> ˇ Von Neumann Architecture (Data and Instruction in the same
> address space).
> ˇ Sixteen, 32 bit General Purpose Registers.
> ˇ Four USER defined instructions (with Register File Write
> back capability).
> ˇ Parallel execution of independent Load/Store, Multiply/Shift ,
> User Defined Instructions and ALU instructions
> (In order issue; Out of order completion)
> ˇ Some Conditional Instructions (Reduces branches & increases
> code density).
> ˇ Built in 32 bit Timer.
> ˇ Power Down Mode.
> ˇ 32x32 Multiplier (Multi cycle execution).
>
> Software Development Tools
> ˇ GNU Assembler, Linker (binutils)
> ˇ GCC (C Compiler)
> ˇ GDB (Debugger) and Instruction Set Simulator
> ˇ Standalone C-Library (RedHat newlib)
> ˇ Modified version of DietLibc
>
> Size and Performance.
>
> Netlists for the current implementation is available for XILINX
> Virtex,Spartan-II and Spartan-IIE; it utilizes 1375 LUTs (809
> slices); the size includes a 32 bit timer and a 32x32 bit LUT
> based multiplier.
>
> The design has been tested to operate at 60MHZ on a Spartan-II
> (speed grade -6).
>
> Netlists, Documentation and Development tools can be downloaded
> from http://www.niktech.com. >
>
> To post a message, send it to:
> To unsubscribe, send a blank message to:
>
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