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Discussion Groups | FPGA-CPU | async SRAM writes
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
async SRAM writes - Jan Gray - Oct 22 23:55:00 2004
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> I must have missed the part in the datasheet dealing with asymetric > timing of read versus write. I have to get back into this as it may > turn out that my system is working, but just because it is slow. > But this is the second time I have seen refereces to multi-clock > timing of writes. I have been treating it like a plain, vanilla, > static ram, 2102 style. OOPS! You might take a closer look at the (too clever by half) write handling in the XSOC design (p. 19 in http://fpgacpu.org/papers/xsoc-series-drafts.pdf), where we use three clock cycles (six clock edges) to perform two writes into an async SRAM. Jan Gray |
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Re: async SRAM writes - rtstofer - Oct 23 3:45:00 2004
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Jan, When I read through your project I was blown away by the elegance of the design. I had tumbled to some of the concepts but I felt it would be a while before I could grasp the entire project. There's just a lot of great ideas. And porting the C compiler was a nice touch - it prompted me to part with the money to buy the book. But, frankly, another RISC or CISC machine didn't really interest me as a project I wanted to build - I can buy one. For nearly 25 years I have had the idea that I wanted to build a Pascal machine. Now that I am retired I have the time to pursue the project and the FPGA technology makes it possible. If I just have enough brains cells left after all these years... And I intend to build an IBM 1130 at some point. I have wanted to do that for 35 years and I had better get it done soon. I don't think a fellow ever forgets his first girl friend or his first computer. I'm still excited about the computer... Richard --- In , "Jan Gray" <jsgray@a...> wrote: > > I must have missed the part in the datasheet dealing with asymetric > > timing of read versus write. I have to get back into this as it may > > turn out that my system is working, but just because it is slow. > > But this is the second time I have seen refereces to multi-clock > > timing of writes. I have been treating it like a plain, vanilla, > > static ram, 2102 style. OOPS! > > You might take a closer look at the (too clever by half) write handling in > the XSOC design (p. 19 in http://fpgacpu.org/papers/xsoc-series- drafts.pdf), > where we use three clock cycles (six clock edges) to perform two writes into > an async SRAM. > > Jan Gray |
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