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Discussion Groups | FPGA-CPU | Driving OFDDRRSE with clk_90
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Driving OFDDRRSE with clk_90 - rtstofer - Oct 27 11:39:00 2004
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The SRAM has a maximum access time of 10 nS and the clock has a period of 20 nS. That seems a little tight using clk_180 to gate ram_we or ram_ce. Could I use clk_90? If so, I would have plenty of margin, no bus contention, life would be good. I'd have 5 nS to get the buffers turned around using my internal MemWR and MemRD signals before strobing ram_ce. I could have searched for a thousand years and not tumbled to the dual rate flop on page 861 of an 1180 page book I haven't even begun to digest! Are there any similar ideas for the Spartan IIE? If so, I could clean up the timing on the T80 core and start to get some serious speed on my CP/M machine. Now, 50 MHz for a Z80 just has to be attractive! Eight times the speed of my CompuPro. Thanks Richard |
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Re: Driving OFDDRRSE with clk_90 - Brian Davis - Oct 27 23:35:00 2004
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rtstofer wrote: > > The SRAM has a maximum access time of 10 nS and the clock has > a period of 20 nS. That seems a little tight using clk_180 > to gate ram_we or ram_ce. > I haven't looked at the detail of the SRAM timing, was just suggesting a way to generate a clock gated strobe without having a race between the address/data clk->q and the clock gating strobe logic. I have one of those S3 boards, but haven't used it yet; a how-fast-can-the-SRAM-go memory test program would be a good test design. > Could I use clk_90? > IIRC, the two clocks into the DDR output register need to be complementary for the magical glitch-free DDR output mux to work; so you could use clk_90 and clk_270 to center the output pulse in the clock cycle, but it would return high before your next clk rising edge, eating up some cycle time on that end. > Are there any similar ideas for the Spartan IIE? > I'd probably use a 2x clock to generate the strobes, or to implement one of the other schemes suggested. If I absolutely HAD to implement clock gating, I'd try something like this: - force the clock gating logic into a single LUT near the related logic and clock/strobe pins: -- use a synthesis directive, or instantiate a LUT4 primitive, to to force the logic into a single LUT -- LOC this LUT4, the global clock input pin, and the gated outputs all near each other on the chip -- apply MAXDELAY constraints to the nets into and out of this LUT4 to help make sure timing is met for glitch and race free output gating If you do this WITHOUT using a DLL, and feed the pre-BUFG input clock over to the LUT4, the global clock insertion & routing delay MIGHT give you enough time to get the trailing edge of the gated clock strobe back off the chip before the address outputs change. ( It's very tough to do this sort of thing properly in Webpack, which doesn't have fpga_editor to look at the implementation. ) Brian p.s. If you plan on putting fast SRAM out on the 'expansion' connectors of the BurchEd or S3 board, be careful: 40 pin connectors with with one ground pin might not play well with sub-ns edge rate CMOS doing data toggle patterns at 50+ MHz. Before trusting any high speed memory on the far side of such a connector, in addition to a really good memory pattern test, I'd also wiggle all the address & data lines 0000/FFFF with the strobes inactive and put a good high bandwidth low Cin scope probe on CE/WE/OE to look for glitches. |
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Re: Driving OFDDRRSE with clk_90 - Brian Davis - Dec 12 21:56:00 2004
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Earlier, I wrote: > > I have one of those S3 boards, but haven't used it yet; >a how-fast-can-the-SRAM-go memory test program would be a >good test design. Following up on this, I've uploaded a first pass at a SRAM tester using a DDR output flip-flop to created a gated write strobe for single-cycle writes to the onboard SRAM of the Xilinx S3 eval kit using only a 1x clock. After first getting a basic count pattern running with the DDR-generated write strobe, I searched around online in hopes of finding an existing SRAM test to modify for the Xilinx S3 board . Although I didn't find one, I did come across Eric Crabill's ZBT tester for his own S3 board at www.fpga-games.com, which inspired the fancier pattern generation now in use. Zip file contents: ftp://members.aol.com/fpgastuff/ram_test.zip : ram_test/post1.txt this post : ram_test/ram_test.vhd ram test code : ram_test/ram_test.ucf constraints file : ram_test/syn_xst/ram_test.npl Xilinx project file Quick notes: - See the header of <ram_test.vhd> for switch/LED functions. ( 25/50 Mhz clock, single-shot/continuous; error, done ) - Hasn't been simulated or verified other than downloading and running on my own S3 board - board level timing hasn't been looked at ( note that S3 timing reports don't include output buffer loading ) - to test idea of tweaking clock duty cycle to make a wider DDR-generated write strobe: it should be possible to create a 33% duty cycle 66 Mhz clock using DCMs by multiplying the onboard 50 MHz up to 200 Mhz, then using the CLKDV output with a CLKDIV_DIVIDE ratio of 1.5 ( most DCM outputs are normally corrected for 50% duty cycle, but the duty cycle changes for DCMs in HIGH frequency mode with small odd fractional divisors ) - per-pass memory pattern rotation not implemented yet ( but those spare counter bits make the LED's blink at a more pleasant rate ) have fun, Brian |
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Re: Driving OFDDRRSE with clk_90 - rtstofer - Dec 13 2:40:00 2004
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Brian, Outstanding - I'll give it a try this week. Richard --- In , "Brian Davis" <brimdavis@a...> wrote: > > Earlier, I wrote: > > > > I have one of those S3 boards, but haven't used it yet; > >a how-fast-can-the-SRAM-go memory test program would be a > >good test design. > > > > Following up on this, I've uploaded a first pass at a SRAM > tester using a DDR output flip-flop to created a gated write > strobe for single-cycle writes to the onboard SRAM of the > Xilinx S3 eval kit using only a 1x clock. > > After first getting a basic count pattern running with > the DDR-generated write strobe, I searched around online > in hopes of finding an existing SRAM test to modify for > the Xilinx S3 board . Although I didn't find one, I did come > across Eric Crabill's ZBT tester for his own S3 board at > www.fpga-games.com, which inspired the fancier pattern > generation now in use. > > Zip file contents: > > ftp://members.aol.com/fpgastuff/ram_test.zip > > : ram_test/post1.txt this post > : ram_test/ram_test.vhd ram test code > : ram_test/ram_test.ucf constraints file > : ram_test/syn_xst/ram_test.npl Xilinx project file > > Quick notes: > > - See the header of <ram_test.vhd> for switch/LED functions. > ( 25/50 Mhz clock, single-shot/continuous; error, done ) > > - Hasn't been simulated or verified other than downloading > and running on my own S3 board > > - board level timing hasn't been looked at ( note that S3 > timing reports don't include output buffer loading ) > > - to test idea of tweaking clock duty cycle to make a wider > DDR-generated write strobe: it should be possible to create > a 33% duty cycle 66 Mhz clock using DCMs by multiplying the > onboard 50 MHz up to 200 Mhz, then using the CLKDV output with > a CLKDIV_DIVIDE ratio of 1.5 ( most DCM outputs are normally > corrected for 50% duty cycle, but the duty cycle changes for > DCMs in HIGH frequency mode with small odd fractional divisors ) > > - per-pass memory pattern rotation not implemented yet ( but those > spare counter bits make the LED's blink at a more pleasant rate ) > > have fun, > Brian |
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