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Discussion Groups | FPGA-CPU | implementing an SMP on an FPGA
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
implementing an SMP on an FPGA - invincible1138 - Nov 12 6:16:00 2004
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Hi all! I am planning to implement an SMP system on a FPGA. I want a ready-made core that i can tweak a little for SMP support and add some glue logic. Later, after synthesizing it on hardware, i want to run an embedded version of linux on it. (Optionally) i would also like to run some code (probably written in C) and use IO to show the results. I am doing this as project in my university and i have about three tofour months to do this. I have done a bit of (a bit of, only) linux kernel compilation stuff and some FPGA programming as well. Digilent's D2FT-DIO5 board is available in university labs https://digilent.us/Sales/Product.cfm?Prod=D2FT-DIO5 which has 300K gates. Now, what my concerns is that is the duration suitable for the project according to my experience level? I mean, can this all be done in three months?? (less/more ??) Secondly, is the board that i have (link above) suitable for implementing a 4-way or higher SMP (atleast 2-way SMP) alongwith some glue logic that i will be adding. For instance, i tihnk Microblaze is too big that even two processors can be programmed on a 300K FPGA as mine. Looking forward for reply. Regards, m n sharif |
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Re: implementing an SMP on an FPGA - rtstofer - Nov 12 16:38:00 2004
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I think if you wander through the Xilinx site you will see where this has been done with the PPC core and some IBM SMP bus protocol. I don't know what size device they used. I am pretty new to FPGA and I don't think there is a chance in the world to pull off a project like this in 3 to 4 months. Now, others on the forum may be able to point you in a direction of work already accomplished. My guess is that the PPC IP will cost a fortune to license. There are a number of nice cores around including the XSOC. This particular core has a huge advantage in that the retargetable C compiler has already been ported so everything is ready to go. I don't know if SMP is possible or even if multiple cores will fit but it would be worth a look. I suppose MicroBlaze is a possibility and it, too, has software support. Licensing is much more reasonable. In fact, I wonder if they would donate it to a university? --- In , "invincible1138" <invincible1138@y...> wrote: > Hi all! > > I am planning to implement an SMP system on a FPGA. > > I want a ready-made core that i can tweak a little for SMP support > and add some glue logic. Later, after synthesizing it on hardware, i > want to run an embedded version of linux on it. (Optionally) i would > also like to run some code (probably written in C) and use IO to show > the results. > I am doing this as project in my university and i have about three > tofour months to do this. I have done a bit of (a bit of, only) linux > kernel compilation stuff and some FPGA programming as well. > Digilent's D2FT-DIO5 board is available in university labs > https://digilent.us/Sales/Product.cfm?Prod=D2FT-DIO5 which has 300K > gates. > > Now, what my concerns is that is the duration suitable for the > project according to my experience level? I mean, can this all be > done in three months?? (less/more ??) > > Secondly, is the board that i have (link above) suitable for > implementing a 4-way or higher SMP (atleast 2-way SMP) alongwith some > glue logic that i will be adding. For instance, i tihnk Microblaze is > too big that even two processors can be programmed on a 300K FPGA as > mine. > > Looking forward for reply. > > Regards, > m n sharif |
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Re: implementing an SMP on an FPGA - invincible1138 - Nov 17 12:49:00 2004
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looking forward for others to enlighten me further !! --- In , "rtstofer" <rstofer@p...> wrote: > I think if you wander through the Xilinx site you will see where > this has been done with the PPC core and some IBM SMP bus protocol. > I don't know what size device they used. > > I am pretty new to FPGA and I don't think there is a chance in the > world to pull off a project like this in 3 to 4 months. Now, others > on the forum may be able to point you in a direction of work already > accomplished. My guess is that the PPC IP will cost a fortune to > license. > > There are a number of nice cores around including the XSOC. This > particular core has a huge advantage in that the retargetable C > compiler has already been ported so everything is ready to go. I > don't know if SMP is possible or even if multiple cores will fit but > it would be worth a look. > > I suppose MicroBlaze is a possibility and it, too, has software > support. Licensing is much more reasonable. In fact, I wonder if > they would donate it to a university? > > --- In , "invincible1138" > <invincible1138@y...> wrote: > > > > > > Hi all! > > > > I am planning to implement an SMP system on a FPGA. > > > > I want a ready-made core that i can tweak a little for SMP support > > and add some glue logic. Later, after synthesizing it on hardware, > i > > want to run an embedded version of linux on it. (Optionally) i > would > > also like to run some code (probably written in C) and use IO to > show > > the results. > > I am doing this as project in my university and i have about three > > tofour months to do this. I have done a bit of (a bit of, only) > linux > > kernel compilation stuff and some FPGA programming as well. > > Digilent's D2FT-DIO5 board is available in university labs > > https://digilent.us/Sales/Product.cfm?Prod=D2FT-DIO5 which has > 300K > > gates. > > > > Now, what my concerns is that is the duration suitable for the > > project according to my experience level? I mean, can this all be > > done in three months?? (less/more ??) > > > > Secondly, is the board that i have (link above) suitable for > > implementing a 4-way or higher SMP (atleast 2-way SMP) alongwith > some > > glue logic that i will be adding. For instance, i tihnk Microblaze > is > > too big that even two processors can be programmed on a 300K FPGA > as > > mine. > > > > Looking forward for reply. > > > > Regards, > > m n sharif |
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