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Discussion Groups | FPGA-CPU | Fwd: Re: IP Redux

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

Fwd: Re: IP Redux - Author Unknown - Nov 25 9:55:00 2004


> >All, please read
> http://www.fpgacpu.org/log/sep02.html#IP-redux.
> Agree?
> >Disagree? Discuss :-)
> >
> >Jan.

Hi all, I've been lurking here for a while; "long time
listener, first time caller". I'm a career developer
of custom logic - ASIC and FPGA for large system
developers. There is much more demand for my FPGA
work these days, for obvious reasons.

My view of the FPGA vendors development of SOPC or
System Builder type tools is that their first
assumption is that FPGA designers are not capable of
engineering their own SOC's, and that the tools must
do it for them.

I think this approach will limit their adoption rate.
I'd rather not offend any who like the IDE tools, as I
am sure there are folks that like these tools.
However, my feeling is that they get in the way when
you really want to do something very specific with the
design. They promote a black box / hands-off /
point-click-ship approach that is not well suited to
fine-tuning designs based on intimate knowledge of
their operation.

I have a question, if IDE SOC development tools are
that important, why didn't they take off years ago in
ASIC design? Folks have been building ASICs with
embedded processors for years, but there are not a lot
of GUI - think it out for you type of tools out there
to build ASIC SOCs.

My two cents,
Chris

=====
________________________________________________________
Chris Schalick
President
Boston Semiconductor, Inc.
(781)775-8897
www.bostonsemiconductor.com
________________________________________________________






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Fwd: Re: IP Redux - rtstofer - Nov 25 12:58:00 2004



Chris,

I agree totally with what you are saying. The point-and-click
design tools serve two purposes: first, it expands the number of
people that can do design work and second, some designs don't need
true artistry.

There are only so many really smart people around and the ones smart
enough to do ASIC or FPGA design with very low level tools are also
smart enough to find a better way to make a living. Why deal with
the pressures of lousy specifications and short schedules when there
are better ways to make money.

So, that shifts the bell curve over and the manufacturers have to
come up with a way for the average engineer to apply their
products. Engineers that aren't and don't want to be specialists in
FPGA - they just want to get the project out the door. Maybe a
simple CPU with a couple of peripherals is all it takes. The FPGA
isn't being used for magic, it is being used for space reduction.
High performance glue.

But the Swiss Army Knife toolkit also gets more people started with
FPGAs; it flattens the learning curve and lowers the entry cost.
One of the big issues I have always had with high end chips was that
I couldn't play with them because I couldn't afford the tools. Now,
thanks to Xilinx WebPack (and similar offerings from others), I can
play with the technology and learn a lot more about logic design.
The problem hasn't gone away: I still can't deal with BGA and some
of the other packages. I have to buy pre-manufactured prototype
boards and some of these are quite pricey. Still, some are quite
reasonable. Especially if the manufacturer is involved - they are
not in the business of selling prototype boards, they want to sell
chips. They can subsidize the boards if it increases chip sales.

Richard

--- In , <cschalick@b...> wrote:
>
> > >All, please read
> > http://www.fpgacpu.org/log/sep02.html#IP-redux.
> > Agree?
> > >Disagree? Discuss :-)
> > >
> > >Jan.
>
> Hi all, I've been lurking here for a while; "long time
> listener, first time caller". I'm a career developer
> of custom logic - ASIC and FPGA for large system
> developers. There is much more demand for my FPGA
> work these days, for obvious reasons.
>
> My view of the FPGA vendors development of SOPC or
> System Builder type tools is that their first
> assumption is that FPGA designers are not capable of
> engineering their own SOC's, and that the tools must
> do it for them.
>
> I think this approach will limit their adoption rate.
> I'd rather not offend any who like the IDE tools, as I
> am sure there are folks that like these tools.
> However, my feeling is that they get in the way when
> you really want to do something very specific with the
> design. They promote a black box / hands-off /
> point-click-ship approach that is not well suited to
> fine-tuning designs based on intimate knowledge of
> their operation.
>
> I have a question, if IDE SOC development tools are
> that important, why didn't they take off years ago in
> ASIC design? Folks have been building ASICs with
> embedded processors for years, but there are not a lot
> of GUI - think it out for you type of tools out there
> to build ASIC SOCs.
>
> My two cents,
> Chris
>
> =====
> ________________________________________________________
> Chris Schalick
> President
> Boston Semiconductor, Inc.
> (781)775-8897
> www.bostonsemiconductor.com
> ________________________________________________________





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