Sign in
Search fpga-cpu
Subscribe to fpga-cpu
fpga-cpu by Keywords
Altera | CISCifying | IDE | ISA | Java | JHDL | JTAG | LBU | MicroBlaze | PAR | PCI | RISC | SoC | Spartan | Transputers | Verilog | VHDL | Virtex | VLIW | WebPack | Xilinx | Xsoc | YARD-1A
Ads
Discussion Groups
See Also
Discussion Groups | FPGA-CPU | Question about Instruction and Data on an FPGA board
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Question about Instruction and Data on an FPGA board - Ben A. Abderazek - Dec 8 1:37:00 2004
|
Dear Helpers, I integrated and generated a netlist for a new processor. I included in the top module two small separate instructions and data memories. My question is, when I will download the "optimized chip" to the Altera STRATIX device, that I already have, do I need to remove these memories or I include them and download the whole chip into the device? Also, I am wondering if I remove these modules how can I test the design later? That, is I need to run some Benchmarks and the binaries must be somewhere! Please notice that the PCI Development kit I have (+ Stratix device) has an SDRAM on it? Thank you so much for your help, /Ben UEC-IS [Non-text portions of this message have been removed] |
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )