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Discussion Groups | FPGA-CPU | Re: FPGA Compiler II + Place and Route

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

FPGA Compiler II + Place and Route - Ben A. Abderazek - Dec 7 20:22:00 2004


Dear Helpers,
I have succeeded to synthesis net list of my processor with FPG compiler II
on a Unix system.

Now when I want to perform "place and route" from the Generated optimized
chip.

I get the following error:
###################################################
Errors
======

FPGA-PLACE-ROUTE-NO-TOOL (1 Occurrence)
Error: Unable to find Quartus place and route tool
#################################################

Can any one tell me what does mean this error?

Please notice that the netlist was generated for ALTERA STRATIX:
EP1S25F1020 device (speed grade C6).
Also I do not have Quartus for Unix., I only have the Quartus II tool
installed in my PC. Do I have to export the netlist and use it in the
Quartus II tool in my PC? Is there is any compatibility problem.
Thank you so much for your help,
/Ben
UEC-IS





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Re: FPGA Compiler II + Place and Route - Marc Nicholas - Dec 7 20:41:00 2004


You need to install Quartus for UNIX.

On Wed, 8 Dec 2004, Ben A. Abderazek wrote: > Dear Helpers,
> I have succeeded to synthesis net list of my processor with FPG compiler II
> on a Unix system.
>
> Now when I want to perform "place and route" from the Generated optimized
> chip.
>
> I get the following error:
> ###################################################
> Errors
> ======
>
> FPGA-PLACE-ROUTE-NO-TOOL (1 Occurrence)
> Error: Unable to find Quartus place and route tool
> #################################################
>
> Can any one tell me what does mean this error?
>
> Please notice that the netlist was generated for ALTERA STRATIX:
> EP1S25F1020 device (speed grade C6).
> Also I do not have Quartus for Unix., I only have the Quartus II tool
> installed in my PC. Do I have to export the netlist and use it in the
> Quartus II tool in my PC? Is there is any compatibility problem.
> Thank you so much for your help,
> /Ben
> UEC-IS >
>
> To post a message, send it to:
> To unsubscribe, send a blank message to:
> Yahoo! Groups Links




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RE: FPGA Compiler II + Place and Route - Jeffery, Robert - Dec 8 4:56:00 2004

Hi Ben.

FPGA Compiler II does not include the vendor place and route tools,
these come form the vendor. If you don't have them installed on your
Unix machine then you need to install them OR take the netlist to your
PC and place and route it there.

Cheers.

Robert.

-----Original Message-----
From: Ben A. Abderazek [mailto:]
Sent: 08 December 2004 01:23
To:
Subject: [fpga-cpu] FPGA Compiler II + Place and Route Dear Helpers,
I have succeeded to synthesis net list of my processor with FPG
compiler II on a Unix system.

Now when I want to perform "place and route" from the Generated
optimized chip.

I get the following error:
###################################################
Errors
======

FPGA-PLACE-ROUTE-NO-TOOL (1 Occurrence)
Error: Unable to find Quartus place and route tool
#################################################

Can any one tell me what does mean this error?

Please notice that the netlist was generated for ALTERA STRATIX:
EP1S25F1020 device (speed grade C6).
Also I do not have Quartus for Unix., I only have the Quartus II tool
installed in my PC. Do I have to export the netlist and use it in the
Quartus II tool in my PC? Is there is any compatibility problem.
Thank you so much for your help,
/Ben
UEC-IS

To post a message, send it to: To unsubscribe,
send a blank message to:
Yahoo! Groups Links



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Re: FPGA Compiler II + Place and Route - Ben A. Abderazek - Dec 8 5:57:00 2004

From: "Jeffery, Robert" <>
>> OR take the netlist to your PC and place and route it there.

Thank you Robert. I got the point. I will export, then, the netlist and try
it on the Altera Quartus II tool.

Do you or other have some recommendation before I proceed. I still have some
wanings from the FPGA compiler II compilation.

Here is one of them:
======================================================================================
Warning: The port '/cpu_bran_io_cc-Optimized/bqu0/O_SUSP' has no driver.
This port will be tied to a logic constant zero.
======================================================================================
Do this and the others warning disturb the place&route later when I do it
on my PC?

Regards
/Ben ----- Original Message -----
From: "Jeffery, Robert" <>
To: <>
Sent: Wednesday, December 08, 2004 6:56 PM
Subject: RE: [fpga-cpu] FPGA Compiler II + Place and Route >
> Hi Ben.
>
> FPGA Compiler II does not include the vendor place and route tools,
> these come form the vendor. If you don't have them installed on your
> Unix machine then you need to install them OR take the netlist to your
> PC and place and route it there.
>
> Cheers.
>
> Robert.
>
> -----Original Message-----
> From: Ben A. Abderazek [mailto:]
> Sent: 08 December 2004 01:23
> To:
> Subject: [fpga-cpu] FPGA Compiler II + Place and Route > Dear Helpers,
> I have succeeded to synthesis net list of my processor with FPG
> compiler II on a Unix system.
>
> Now when I want to perform "place and route" from the Generated
> optimized chip.
>
> I get the following error:
> ###################################################
> Errors
> ======
>
> FPGA-PLACE-ROUTE-NO-TOOL (1 Occurrence)
> Error: Unable to find Quartus place and route tool
> #################################################
>
> Can any one tell me what does mean this error?
>
> Please notice that the netlist was generated for ALTERA STRATIX:
> EP1S25F1020 device (speed grade C6).
> Also I do not have Quartus for Unix., I only have the Quartus II tool
> installed in my PC. Do I have to export the netlist and use it in the
> Quartus II tool in my PC? Is there is any compatibility problem.
> Thank you so much for your help,
> /Ben
> UEC-IS
>
> To post a message, send it to: To unsubscribe,
> send a blank message to:
> Yahoo! Groups Links
>
> To post a message, send it to:
> To unsubscribe, send a blank message to:
>
> Yahoo! Groups Links



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Re: FPGA Compiler II + Place and Route - Ben A. Abderazek - Dec 8 6:16:00 2004

> FPGA Compiler II does not include the vendor place and route tools,
> these come form the vendor

I did that on FPGA compiler II when I right clicked on the Optimized-chip, I
found the option "plcae and route". I though I can perform place an route.
Do you know what are/is the tool(s) of Synopsis (FPGA compiler II) that
perform place and route?
I actually wanted to export the netlist and use it in Quartus II on my PC
that alse also have a PCI developmnet kit on IT.
Please explain if possible, whihc is better: install the tools on the Unix
System and perform Place and route then export to PC env. for configuration
OR export the netlist and use the Quartus II tools on my PC then downlod the
code into the FPGA device on the PCI development Kit that I have already?

Many thanks again Robert,
/Ben
----- Original Message -----
From: "Jeffery, Robert" <>
To: <>
Sent: Wednesday, December 08, 2004 6:56 PM
Subject: RE: [fpga-cpu] FPGA Compiler II + Place and Route >
> Hi Ben.
>
> FPGA Compiler II does not include the vendor place and route tools,
> these come form the vendor. If you don't have them installed on your
> Unix machine then you need to install them OR take the netlist to your
> PC and place and route it there.
>
> Cheers.
>
> Robert.
>
> -----Original Message-----
> From: Ben A. Abderazek [mailto:]
> Sent: 08 December 2004 01:23
> To:
> Subject: [fpga-cpu] FPGA Compiler II + Place and Route > Dear Helpers,
> I have succeeded to synthesis net list of my processor with FPG
> compiler II on a Unix system.
>
> Now when I want to perform "place and route" from the Generated
> optimized chip.
>
> I get the following error:
> ###################################################
> Errors
> ======
>
> FPGA-PLACE-ROUTE-NO-TOOL (1 Occurrence)
> Error: Unable to find Quartus place and route tool
> #################################################
>
> Can any one tell me what does mean this error?
>
> Please notice that the netlist was generated for ALTERA STRATIX:
> EP1S25F1020 device (speed grade C6).
> Also I do not have Quartus for Unix., I only have the Quartus II tool
> installed in my PC. Do I have to export the netlist and use it in the
> Quartus II tool in my PC? Is there is any compatibility problem.
> Thank you so much for your help,
> /Ben
> UEC-IS >
>
> To post a message, send it to: To unsubscribe,
> send a blank message to:
> Yahoo! Groups Links >
> To post a message, send it to:
> To unsubscribe, send a blank message to:
>
> Yahoo! Groups Links



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RE: FPGA Compiler II + Place and Route - Jeffery, Robert - Dec 8 6:21:00 2004

Hi Ben.

Without knowing the design it's difficult to say. The question you need
to ask yourself is:

"Does this message make sense? What am I expecting this signal to do?
Right now it's not being driven by anything. Is it a dangling component
port or hierarchical port?"

Running through Quartus may give you further messages or more likely
Quartus will just throw it away but really you need to understand why
FPGA Compiler is giving you the message in the first place. I believe
you should be able to cross probe with the Synopsys tool and that may
help you.

Cheers.

Robert.

-----Original Message-----
From: Ben A. Abderazek [mailto:]
Sent: 08 December 2004 10:57
To:
Subject: Re: [fpga-cpu] FPGA Compiler II + Place and Route From: "Jeffery, Robert" <>
>> OR take the netlist to your PC and place and route it there.

Thank you Robert. I got the point. I will export, then, the netlist and
try it on the Altera Quartus II tool.

Do you or other have some recommendation before I proceed. I still have
some wanings from the FPGA compiler II compilation.

Here is one of them:
========================================================================
==============
Warning: The port '/cpu_bran_io_cc-Optimized/bqu0/O_SUSP' has no
driver.
This port will be tied to a logic constant zero.
========================================================================
==============
Do this and the others warning disturb the place&route later when I do
it on my PC?

Regards
/Ben ----- Original Message -----
From: "Jeffery, Robert" <>
To: <>
Sent: Wednesday, December 08, 2004 6:56 PM
Subject: RE: [fpga-cpu] FPGA Compiler II + Place and Route >
> Hi Ben.
>
> FPGA Compiler II does not include the vendor place and route tools,
> these come form the vendor. If you don't have them installed on your
> Unix machine then you need to install them OR take the netlist to your
> PC and place and route it there.
>
> Cheers.
>
> Robert.
>
> -----Original Message-----
> From: Ben A. Abderazek [mailto:]
> Sent: 08 December 2004 01:23
> To:
> Subject: [fpga-cpu] FPGA Compiler II + Place and Route > Dear Helpers,
> I have succeeded to synthesis net list of my processor with FPG
> compiler II on a Unix system.
>
> Now when I want to perform "place and route" from the Generated
> optimized chip.
>
> I get the following error:
> ###################################################
> Errors
> ======
>
> FPGA-PLACE-ROUTE-NO-TOOL (1 Occurrence)
> Error: Unable to find Quartus place and route tool
> #################################################
>
> Can any one tell me what does mean this error?
>
> Please notice that the netlist was generated for ALTERA STRATIX:
> EP1S25F1020 device (speed grade C6).
> Also I do not have Quartus for Unix., I only have the Quartus II tool
> installed in my PC. Do I have to export the netlist and use it in the
> Quartus II tool in my PC? Is there is any compatibility problem.
> Thank you so much for your help,
> /Ben
> UEC-IS
>
> To post a message, send it to: To
unsubscribe,
> send a blank message to:
> Yahoo! Groups Links
>
> To post a message, send it to:
> To unsubscribe, send a blank message to:
>
> Yahoo! Groups Links
To post a message, send it to:
To unsubscribe, send a blank message to:

Yahoo! Groups Links



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RE: FPGA Compiler II + Place and Route - Jeffery, Robert - Dec 8 6:25:00 2004

Hi Ben.

FPGA Compiler doesn't have any place and route capability. All that menu
picking is doing is starting up Quartus for you and passing the design
across and setting up a project in Quartus. Bottom line is that you need
Quartus on Unix since that's where you are running FPGA Compiler II or
you need to put the netlist on your PC and run the Quartus yourself.

You should try a Mentor Graphics synthesis tool like Precision that runs
on PC :) (Sorry Jan I couldn't resist)

Cheers.

Robert.

-----Original Message-----
From: Ben A. Abderazek [mailto:]
Sent: 08 December 2004 11:16
To:
Subject: Re: [fpga-cpu] FPGA Compiler II + Place and Route > FPGA Compiler II does not include the vendor place and route tools,
> these come form the vendor

I did that on FPGA compiler II when I right clicked on the
Optimized-chip, I found the option "plcae and route". I though I can
perform place an route.
Do you know what are/is the tool(s) of Synopsis (FPGA compiler II) that
perform place and route?
I actually wanted to export the netlist and use it in Quartus II on my
PC that alse also have a PCI developmnet kit on IT.
Please explain if possible, whihc is better: install the tools on the
Unix System and perform Place and route then export to PC env. for
configuration OR export the netlist and use the Quartus II tools on my
PC then downlod the code into the FPGA device on the PCI development Kit
that I have already?

Many thanks again Robert,
/Ben
----- Original Message -----
From: "Jeffery, Robert" <>
To: <>
Sent: Wednesday, December 08, 2004 6:56 PM
Subject: RE: [fpga-cpu] FPGA Compiler II + Place and Route >
> Hi Ben.
>
> FPGA Compiler II does not include the vendor place and route tools,
> these come form the vendor. If you don't have them installed on your
> Unix machine then you need to install them OR take the netlist to your
> PC and place and route it there.
>
> Cheers.
>
> Robert.
>
> -----Original Message-----
> From: Ben A. Abderazek [mailto:]
> Sent: 08 December 2004 01:23
> To:
> Subject: [fpga-cpu] FPGA Compiler II + Place and Route > Dear Helpers,
> I have succeeded to synthesis net list of my processor with FPG
> compiler II on a Unix system.
>
> Now when I want to perform "place and route" from the Generated
> optimized chip.
>
> I get the following error:
> ###################################################
> Errors
> ======
>
> FPGA-PLACE-ROUTE-NO-TOOL (1 Occurrence)
> Error: Unable to find Quartus place and route tool
> #################################################
>
> Can any one tell me what does mean this error?
>
> Please notice that the netlist was generated for ALTERA STRATIX:
> EP1S25F1020 device (speed grade C6).
> Also I do not have Quartus for Unix., I only have the Quartus II tool
> installed in my PC. Do I have to export the netlist and use it in the
> Quartus II tool in my PC? Is there is any compatibility problem.
> Thank you so much for your help,
> /Ben
> UEC-IS >
>
> To post a message, send it to: To
unsubscribe,
> send a blank message to:
> Yahoo! Groups Links >
> To post a message, send it to:
> To unsubscribe, send a blank message to:
>
> Yahoo! Groups Links
To post a message, send it to:
To unsubscribe, send a blank message to:

Yahoo! Groups Links




(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )

RE: FPGA Compiler II + Place and Route - Author Unknown - Dec 8 7:43:00 2004

I strongly encourage you to try the synthesis tool
built in to Quartus. You may find that it is not
adequate for your needs, but you will not have any
compatibility issues with the netlist working with the
place and route tool (they're the same tool).

I find that for most designs the built in synthesis
tool is just fine, and produces results within 10% of
Synplify in both area and timing.

On a similar note, the Xilinx tools have a built in
synthesis tool (XST) if you want to target a different
device.

FPGA Compiler is not known as the best FPGA synthesis
tool available, as their ASIC synthesis tools are.
That trophy belongs to Synplicity and Mentor.

Chris

--- "Jeffery, Robert" <>
wrote: > Hi Ben.
>
> FPGA Compiler doesn't have any place and route
> capability. All that menu
> picking is doing is starting up Quartus for you and
> passing the design
> across and setting up a project in Quartus. Bottom
> line is that you need
> Quartus on Unix since that's where you are running
> FPGA Compiler II or
> you need to put the netlist on your PC and run the
> Quartus yourself.
>
> You should try a Mentor Graphics synthesis tool like
> Precision that runs
> on PC :) (Sorry Jan I couldn't resist)
>
> Cheers.
>
> Robert.
>
> -----Original Message-----
> From: Ben A. Abderazek
> [mailto:]
> Sent: 08 December 2004 11:16
> To:
> Subject: Re: [fpga-cpu] FPGA Compiler II + Place and
> Route > > FPGA Compiler II does not include the vendor place
> and route tools,
> > these come form the vendor
>
> I did that on FPGA compiler II when I right clicked
> on the
> Optimized-chip, I found the option "plcae and
> route". I though I can
> perform place an route.
> Do you know what are/is the tool(s) of Synopsis
> (FPGA compiler II) that
> perform place and route?
> I actually wanted to export the netlist and use it
> in Quartus II on my
> PC that alse also have a PCI developmnet kit on IT.
> Please explain if possible, whihc is better: install
> the tools on the
> Unix System and perform Place and route then export
> to PC env. for
> configuration OR export the netlist and use the
> Quartus II tools on my
> PC then downlod the code into the FPGA device on the
> PCI development Kit
> that I have already?
>
> Many thanks again Robert,
> /Ben >
> ----- Original Message -----
> From: "Jeffery, Robert" <>
> To: <>
> Sent: Wednesday, December 08, 2004 6:56 PM
> Subject: RE: [fpga-cpu] FPGA Compiler II + Place and
> Route > >
> > Hi Ben.
> >
> > FPGA Compiler II does not include the vendor place
> and route tools,
> > these come form the vendor. If you don't have them
> installed on your
> > Unix machine then you need to install them OR take
> the netlist to your
> > PC and place and route it there.
> >
> > Cheers.
> >
> > Robert.
> >
> > -----Original Message-----
> > From: Ben A. Abderazek
> [mailto:]
> > Sent: 08 December 2004 01:23
> > To:
> > Subject: [fpga-cpu] FPGA Compiler II + Place and
> Route
> >
> >
> > Dear Helpers,
> > I have succeeded to synthesis net list of my
> processor with FPG
> > compiler II on a Unix system.
> >
> > Now when I want to perform "place and route" from
> the Generated
> > optimized chip.
> >
> > I get the following error:
> >
> ###################################################
> > Errors
> > ======
> >
> > FPGA-PLACE-ROUTE-NO-TOOL (1 Occurrence)
> > Error: Unable to find Quartus place and
> route tool
> > #################################################
> >
> > Can any one tell me what does mean this error?
> >
> > Please notice that the netlist was generated for
> ALTERA STRATIX:
> > EP1S25F1020 device (speed grade C6).
> > Also I do not have Quartus for Unix., I only have
> the Quartus II tool
> > installed in my PC. Do I have to export the
> netlist and use it in the
> > Quartus II tool in my PC? Is there is any
> compatibility problem.
> > Thank you so much for your help,
> > /Ben
> > UEC-IS
> >
> >
> >
> >
> > To post a message, send it to:
> To
> unsubscribe,
> > send a blank message to:
>
> > Yahoo! Groups Links
> >
> >
> >
> >
> >
> >
> >
> >
> >
> > To post a message, send it to:
>
> > To unsubscribe, send a blank message to:
> >
> > Yahoo! Groups Links
> >
> >
> >
> >
> >
> >
> >
> >
>
> To post a message, send it to:
>
> To unsubscribe, send a blank message to:
>
> Yahoo! Groups Links >
> To post a message, send it to:
>
> To unsubscribe, send a blank message to:
>
> Yahoo! Groups Links =====
________________________________________________________
Chris Schalick
President
Boston Semiconductor, Inc.
(781)775-8897
www.bostonsemiconductor.com
________________________________________________________


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RE: FPGA Compiler II + Place and Route - Austin Franklin - Dec 8 9:48:00 2004

Hi Chris,

> FPGA Compiler is not known as the best FPGA synthesis
> tool available, as their ASIC synthesis tools are.
> That trophy belongs to Synplicity and Mentor.

Which Mentor FPGA synthesis tool do you believe to be on par with Synplify?

Regards,

Austin




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Re: FPGA Compiler II + Place and Route - ben franchuk - Dec 8 11:41:00 2004

Austin Franklin wrote:
> Which Mentor FPGA synthesis tool do you believe to be on par with Synplify?

Well I would rate tools this way.
1) What you can afford.
2) Correct synthesis.
3) Logic fits in the FPGA
4) Speed.

For a person who's hobby is simple CPU design rather that leading
edge RISK(y) machines I have gone back to TTL logic since I
think graphics as in schematics rather than programing logic.
Also with the older FPGA development board - altera 10K I was
having problems with item 3. Rather than get a new FPGA protype
board TTL logic is a better way for the One-Off prototype developmemt
I am doing.
Ben.






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RE: FPGA Compiler II + Place and Route - Austin Franklin - Dec 8 12:12:00 2004

Hi Ben,

You can always instantiate anything you want in synthesis to make it as
compact/speedy as you want to...so technically, if you put the work into it,
synthesis (which is a misnomer if you are really instantiating everything
;-) will be on par with schematics. But, if you are not instantiating, then
yes, I agree, you will have more control with schematics...but that requires
a proprietary schematic capture program, and developing symbol libraries,
which has problems unto it self.

Regards,

Austin > Austin Franklin wrote:
> > Which Mentor FPGA synthesis tool do you believe to be on par
> with Synplify?
>
> Well I would rate tools this way.
> 1) What you can afford.
> 2) Correct synthesis.
> 3) Logic fits in the FPGA
> 4) Speed.
>
> For a person who's hobby is simple CPU design rather that leading
> edge RISK(y) machines I have gone back to TTL logic since I
> think graphics as in schematics rather than programing logic.
> Also with the older FPGA development board - altera 10K I was
> having problems with item 3. Rather than get a new FPGA protype
> board TTL logic is a better way for the One-Off prototype developmemt
> I am doing.
> Ben.





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RE: FPGA Compiler II + Place and Route - Author Unknown - Dec 8 12:16:00 2004

Well I may be off-base here but I though Leonardo was
a Mentor tool. I remember fairly recent discussions
about market share being extremely close between that
tool and Synplify. I extrapolated that to mean that
the tools are of comparable quality.

However, I have never used Leonardo so I can't speak
from experience. I was only trying not to offend any
Leonardo - officionados, if there are any lurking
about.

Chris

--- Austin Franklin <> wrote: > Hi Ben,
>
> You can always instantiate anything you want in
> synthesis to make it as
> compact/speedy as you want to...so technically, if
> you put the work into it,
> synthesis (which is a misnomer if you are really
> instantiating everything
> ;-) will be on par with schematics. But, if you are
> not instantiating, then
> yes, I agree, you will have more control with
> schematics...but that requires
> a proprietary schematic capture program, and
> developing symbol libraries,
> which has problems unto it self.
>
> Regards,
>
> Austin > > Austin Franklin wrote:
> > > Which Mentor FPGA synthesis tool do you believe
> to be on par
> > with Synplify?
> >
> > Well I would rate tools this way.
> > 1) What you can afford.
> > 2) Correct synthesis.
> > 3) Logic fits in the FPGA
> > 4) Speed.
> >
> > For a person who's hobby is simple CPU design
> rather that leading
> > edge RISK(y) machines I have gone back to TTL
> logic since I
> > think graphics as in schematics rather than
> programing logic.
> > Also with the older FPGA development board -
> altera 10K I was
> > having problems with item 3. Rather than get a
> new FPGA protype
> > board TTL logic is a better way for the One-Off
> prototype developmemt
> > I am doing.
> > Ben. >
>
> To post a message, send it to:
>
> To unsubscribe, send a blank message to:
>
> Yahoo! Groups Links =====
________________________________________________________
Chris Schalick
President
Boston Semiconductor, Inc.
(781)775-8897
www.bostonsemiconductor.com
________________________________________________________


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RE: FPGA Compiler II + Place and Route - Austin Franklin - Dec 8 12:27:00 2004

Hi Chris,

> Well I may be off-base here but I though Leonardo was
> a Mentor tool. I remember fairly recent discussions
> about market share being extremely close between that
> tool and Synplify. I extrapolated that to mean that
> the tools are of comparable quality.

I'm not sure that metric is a good one...without knowing the costs for one.
I think Leonardo may be much cheaper, which may account for it's
"popularity". I know Synplify is not cheap these days.

And yes, I do believe Leonardo is a Mentor product now.

Regards,

Austin





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RE: FPGA Compiler II + Place and Route - Author Unknown - Dec 8 14:34:00 2004

In any event, the Synposys tools have historically
under-performed.

I think they are making a big push with a re-write of
their tools, but I think the jury is still out on
that.

Chris

--- Austin Franklin <> wrote: > Hi Chris,
>
> > Well I may be off-base here but I though Leonardo
> was
> > a Mentor tool. I remember fairly recent
> discussions
> > about market share being extremely close between
> that
> > tool and Synplify. I extrapolated that to mean
> that
> > the tools are of comparable quality.
>
> I'm not sure that metric is a good one...without
> knowing the costs for one.
> I think Leonardo may be much cheaper, which may
> account for it's
> "popularity". I know Synplify is not cheap these
> days.
>
> And yes, I do believe Leonardo is a Mentor product
> now.
>
> Regards,
>
> Austin >
>
> To post a message, send it to:
>
> To unsubscribe, send a blank message to:
>
> Yahoo! Groups Links =====
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Re: FPGA Compiler II + Place and Route - Jeff Brower - Dec 8 14:39:00 2004

Austin-

> That always surprised me that [Synopsis] have the best in class ASIC tools, but
> had a really crappy, overpriced FPGA synthesis tool, and didn't seem to
> care.

<blab>Things like EasyPath will force changes in that attitude:

http://www.xilinx.com/products/easypath/index.htm

These are embryonic and experimental efforts. But at some point, today's "layout"
will be the FPGA, "PCB fab" will be sending in your bit file and getting back a
stripped-down low-cost chip, and assembly will be adding power, gnd, and connectors
;-)

</blab>

-Jeff


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RE: FPGA Compiler II + Place and Route - Austin Franklin - Dec 8 14:57:00 2004

Hi Chris,

> In any event, the Synposys tools have historically
> under-performed.

Absolutely! And especially for the price.

> I think they are making a big push with a re-write of
> their tools, but I think the jury is still out on
> that.

That always surprised me that they have the best in class ASIC tools, but
had a really crappy, overpriced FPGA synthesis tool, and didn't seem to
care.

Regards,

Austin




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Re: FPGA Compiler II + Place and Route - Jeff Brower - Dec 8 15:30:00 2004

Austin-

> My experience with any FPGA conversions over the 17 years I've been
> designing FPGAs and ASICs is that people talk a lot about doing FPGA
> conversions, try to plan for them, but never actually do them. Now,
> EasyPath may be different, but I've never had a request for one...yet.

The idea behind EasyPath is that the FPGA chip vendor does the conversion; i.e. the
same vendor supplies both chips. If that really turns out to work, then yes it
should shake things up, including tools.

-Jeff

> > -----Original Message-----
> > From: Jeff Brower [mailto:]
> > Sent: Wednesday, December 08, 2004 2:39 PM
> > To:
> > Subject: Re: [fpga-cpu] FPGA Compiler II + Place and Route
> >
> >
> >
> > Austin-
> >
> > > That always surprised me that [Synopsis] have the best in class
> > ASIC tools, but
> > > had a really crappy, overpriced FPGA synthesis tool, and didn't seem to
> > > care.
> >
> > <blab>Things like EasyPath will force changes in that attitude:
> >
> > http://www.xilinx.com/products/easypath/index.htm
> >
> > These are embryonic and experimental efforts. But at some point,
> > today's "layout"
> > will be the FPGA, "PCB fab" will be sending in your bit file and
> > getting back a
> > stripped-down low-cost chip, and assembly will be adding power,
> > gnd, and connectors
> > ;-)
> >
> > </blab>
> >
> > -Jeff


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Re: FPGA Compiler II + Place and Route - Jeff Brower - Dec 8 16:00:00 2004

Austin-

> That was true before as well, it was called "hardwire". They simply
> replaced the SRAM configuration memory with a fixed mask. There were some
> companies that did FPGA conversions as a service as well, but as I said,
> IME, none of my clients ever actually did the either of these.

Ok I see it now, first introduced in 1997. Well at least they keep trying.

> Again, why (for both)? Hardwire was available previously, and never really
> went anywhere, and I don't see how the front end tools are effected by this
> "conversion" process.

It would only matter if it really worked well and caught on. Evidently HardWire did
not work well, or did not provide significant cost/benefit advantage, which makes me
wonder what Xilinx is doing differently this time around.

-Jeff





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Re: FPGA Compiler II + Place and Route - Jeff Brower - Dec 9 11:30:00 2004

Austin-

> > Easypath is not using scrap devices, it's using new devices.
>
> Could these new devices be sold as new "regular" devices? If not, then what
> would happen to them if there were no "EasyPath" offering?

If Xilinx could "zap" portions of the silicon not used by the customer's design to
reduce power consumption (which they don't, but wouldn't it be nice), and that
portion happened to have the error, would you still consider the initial device
scrap?

I think the concept of scrap is less relevant for a device intended to be configured
differently for every customer. For an IC manufacturer that wants to get away with a
simple data sheet and no development tools, ya any little problem makes the device
scrap. But for a manufacturer with 10s of mils invested in tools, support, core
development, etc it's not the same. If they can get some of the investment back by
finding more ways to work around silicon flaws, that's powerful.

-Jeff


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Re: FPGA Compiler II + Place and Route - Kolja Sulimma - Dec 9 11:57:00 2004

On Thu, 2004-12-09 at 17:19, Göran Bilski wrote:
> Hi,
>
> Easypath is not using scrap devices, it's using new devices.
Yes, new defective devices. But with defects that do not bother the
specific customer.

> The biggest gain and therefor cost reduction is the increased yield.
Last time I checked increased yield meant less devices are send to the
garbage can.

> On large FPGA, one single bad routing connections will make the device
> faulty but the chance that one faulty routing connection on a FPGA will
> make ONE particular design faulty is small.
> So the yield is increased, the larger device the more increased yield.

Yes, so a device that fails testing because of a single failure can be
sold as an easypath device, but would go to the landfill without
easypath.

That's exactly what I said.

I think it is a very clever approach and there is nothing wrong with it.
But it is still true that as long as there are more devices failing
testing because of a small number of faults than there are easypath
orders the device cost is essentially zero (plus testing and packaging).

And I think you underestimate the intelligence of your colleages at
xilinx if you expect them to test untested device against my easypath
specification. I am sure they test devices that failed the general
testing first.

Kolja Sulimma




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Re: FPGA Compiler II + Place and Route - Jeff Brower - Dec 10 6:28:00 2004

Paul-

> (1) As I've said previously, don't expect a free ride forever; Xilinx
> will pull the plug when their 95nm yields increase; and

Does the day come when it actually IS cheaper for Xilinx to provide volume devices to
a customer that uses 1/2 the logic, or doesn't use some pins or certain chip
functions?

Is there a time when it's actually a viable, long-term product model that competes
with ASICs and is not based on (temporarily) low yields?

-Jeff


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Re: FPGA Compiler II + Place and Route - Jeff Brower - Dec 10 11:17:00 2004

Paul-

Thanks that one is a keeper. I have forwarded it internally to our engineers.

-Jeff Paul Davis wrote:
>
> Jeff Brower wrote:
>
> > Paul-
> >
> >
> >>(1) As I've said previously, don't expect a free ride forever; Xilinx
> >>will pull the plug when their 95nm yields increase; and
> >
> >
> > Does the day come when it actually IS cheaper for Xilinx to provide volume devices to
> > a customer that uses 1/2 the logic, or doesn't use some pins or certain chip
> > functions?
> >
> > Is there a time when it's actually a viable, long-term product model that competes
> > with ASICs and is not based on (temporarily) low yields?
>
> No, IMHO, for 2 main reasons (unless, of course, you don't have the
> volumes to justify the NREs):
>
> 1) Foundry pricing is very simple: you pay per square mm. When placing
> your logic on an FPGA, you probably use 2.5 times as much area (your
> guess?) as you do on standard-cell, hence 2.5 times the base cost
> (remember there are two factors here: the inefficiency of programmable
> logic, and the fact that you have to buy the die size that Xilinx
> manufactures, and not the die size that you actually want).
>
> 2) Xilinx runs on 64% gross margins
> (http://www.reed-electronics.com/electronicnews/article/CA486500?nid=2019).
> This means that, if their *only* cost was silicon from the foundry, then
> they're marking up their silicon by a factor of 2.8. Of course, they've
> got lots of other costs, so they're probably marking up by a factor of
> (your guess?) maybe 5.
>
> Conclusion: if you do standard cell, you pay the foundry $n per chip; if
> you buy an FPGA, you instead pay Xilinx (2.5*5)n = $12.5n per chip,
> ignoring the cost of storing the bitstream, and supplying the extra
> power, and getting rid of the extra heat, and the cost of all the analog
> bits that you could have mopped up if you'd actually done an ASIC, and
> the hidden costs of having a 95nm device on your board when your app
> only actually needed 130 or 250nm, and all the rest of it.
>
> So, averaging across all designs and all FPGA devices, you pay Xilinx
> $12.50 instead of paying the foundry $1.00. That's my estimate, anyway.
> Xilinx probably gives you a better deal on the small devices, to get you
> on board, and then takes the hit on the bigger devices. But what's the
> better deal? If you're using an old Spartan, are you paying $6 instead
> of $1? Or $8?
>
> Anyway, if you want a good deal from Xilinx, just ask them. See the
> article above - they've got a huge inventory, sales are falling, they've
> just lowered guidance for this quarter, and everyone seems to think that
> we're into the next downturn, so it's not going to get better quickly.
> Tell your rep you need a 20% discount, keep a straight face, and it'll
> probably work...
>
> :)





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Re: FPGA Compiler II + Place and Route - ben franchuk - Dec 10 11:20:00 2004

Paul Davis wrote:

> (2) This one is just a hunch; I'm not a process engineer. Xilinx is
> probably only getting about 97% coverage on their original structural
> test. If a part fails this test, but then passes on a customer's
> functional test, is it then more likely that there's an undetected
> failure on the remaining 3% of the original structural test, which also
> managed to slip through the customer's functional test? I think there
> probably is. In other words, when doing your own (customer) board yield
> calculations, you may have to factor in that these parts are not as good
> as they might appear to be.

But there at at least 2 kinds of error that I see.
1) Hardware fault -- broken wire, transistor ect.
2) Die fabrication fault. Transistors don't have the
rated speed or drive in that section of the chip.
In case #1 you don't have a problem since you don't use that
part of the chip. In case #2 your design may not need the
full specs on that part since it may not be in a critical timing path.
In both cases you still get 100% functionalty, providing you
don't change your design often.
Ben.



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