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Discussion Groups | FPGA-CPU | RE: Xilinx bitgen problem
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Xilinx bitgen problem - Bharath Kumar - Jan 4 3:58:00 2001
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hi All, I tried my first design using design manager yesterday... I was able to succesfully complete the flow upto Place and Route(PAR).... but "Bitgen" is giving some problem as follows: ************************************************************************************* Running DRC ERROR:DesignRules:368 - Netcheck: Sourceless. Net clk has no source. ERROR:DesignRules:10 - Netcheck: The signal "clk" is completely unrouted. ***************************************************************************************** I couldnt get the exact meaning of the above message...Please help me. thanks and Regards, Bharath Bangalore, INDIA [Non-text portions of this message have been removed] |
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Re: Xilinx bitgen problem - Guilherme Jorge - Jan 4 20:04:00 2001
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Hi! Maybe what I'm going to said is stupid, but "the clk has no source".... What clk is that??? Are you using the fpga external clock??? If you are not, I think you my try it, by using pin 13. That's what I think... sorry if it's dumb... hehe ;P Thanks for listening... Jorge, Guilherme ----- Original Message ----- From: "Bharath Kumar" <> To: <> Sent: Thursday, January 04, 2001 6:58 AM Subject: [fpga-cpu] Xilinx bitgen problem > hi All, > I tried my first design using design manager yesterday... > I was able to succesfully complete the flow upto Place and Route(PAR).... but > "Bitgen" is giving some problem as follows: > **************************************************************************** ********* > Running DRC > ERROR:DesignRules:368 - Netcheck: Sourceless. Net clk has no source. > ERROR:DesignRules:10 - Netcheck: The signal "clk" is completely unrouted. > **************************************************************************** ************* > > I couldnt get the exact meaning of the above message...Please help me. > > thanks and Regards, > Bharath > Bangalore, INDIA > > > [Non-text portions of this message have been removed] > To Post a message, send it to: > To Unsubscribe, send a blank message to: |
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RE: Xilinx bitgen problem - Jan Gray - Jan 5 0:00:00 2001
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It appears that you are using a net, clk, that has no driver. I assume you hope to use an external clock signal. You must bring it into the device (and reflect that in your design). In schematics, you instantiate an IPAD and connect it to an IBUF, and connect that to a BUFGP/BUFGS/BUFG. For one example, open the XSOC schematics in the Foundation editor, and/or review /xsoc/doc/schematics.pdf in the XSOC Project Kit (via www.fpgacpu.org/xsoc/). In HDL, you need to declare clk as an input and use it as a synchronous control signal (e.g. module foo(clk, ...) input clk; ... always @(posedge clk) ... endmodule ) and that should suffice for the synthesis tool to infer it as a clock input and provide the BUFG on your behalf. I recommend working through Dave Vanden Bout's 'Practical Xilinx Designer Lab Book' exercises for a tutorial introduction to all these beginning Xilinx issues. Jan Gray, Gray Research LLC |
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Re: Xilinx bitgen problem - Bharath Kumar - Jan 5 5:13:00 2001
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Hi Mr.Jan, Thank you very much for replying... Now i am realising that I have some problem in the synthesis itself... Let me explain what's happening in my design.. I have a modules A and B. The module B is instantiated in module A. As you rightly said, the clock is an external signal. verilog code is as follows module A( clk, data,.........); input clk; . . . B b1 (clk,abc,......); .... .. .. endmodule module B (clk,abc......); input clk; always @(posedge clk) begin .... ... end .... endmodule *** In brief, i am simply passing signal 'clk' from module A ( which is the top module) to module B. Since there is no " always @ (posedge clk) " in the module A, the synthesis tool is not able to infer I/o buffer or pad... Am I right?????? *** If I instantiate a buffer component of xilinx in the RTL... Then it becomes Xilinx dependent. According to my knowledge, RTL should be technology independent. *** How to circumvent this problem...???? *** I am using Synopsys Design Compiler 1999.10 for synthesis and ' EDIF ' from this i am giving to Xilinx design manager... Pls help me. thanks, Bharath Bangalore, INDIA ----- Original Message ----- From: Jan Gray <> To: <> Sent: Friday, January 05, 2001 10:30 AM Subject: RE: [fpga-cpu] Xilinx bitgen problem > It appears that you are using a net, clk, that has no driver. I assume you > hope to use an external clock signal. You must bring it into the device > (and reflect that in your design). > > In schematics, you instantiate an IPAD and connect it to an IBUF, and > connect that to a BUFGP/BUFGS/BUFG. For one example, open the XSOC > schematics in the Foundation editor, and/or review /xsoc/doc/schematics.pdf > in the XSOC Project Kit (via www.fpgacpu.org/xsoc/). > > In HDL, you need to declare clk as an input and use it as a synchronous > control signal (e.g. > module foo(clk, ...) > input clk; ... > always @(posedge clk) ... > endmodule > ) > and that should suffice for the synthesis tool to infer it as a clock input > and provide the BUFG on your behalf. > > I recommend working through Dave Vanden Bout's 'Practical Xilinx Designer > Lab Book' exercises for a tutorial introduction to all these beginning > Xilinx issues. > > Jan Gray, Gray Research LLC > To Post a message, send it to: > To Unsubscribe, send a blank message to: |
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Re: Xilinx bitgen problem - Mike Butts - Jan 5 14:31:00 2001
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Hi, Bharath! I think I know what's going on. Your Verilog is correct. FPGA Compiler II, FPGA Express, or the synthesis in the Xilinx Student Edition (which is FPGA Express) will infer the right IBUF/BUFGP/BUFGS/BUFG combination for your target architecture into the EDIF file, and drive your clk net. > *** I am using Synopsys Design Compiler 1999.10 for synthesis Design Compiler is a generic synthesis tool for ASICs, FPGAs or anything. It's optimized for ASICs and full custom designs. It won't infer the IOBs on its own without being told to somehow. You'd have to use DC with the -fpga switch (I think that's what the switch is called, double-check) and maybe also tell it, with a command or a dc_shell script entry, to infer IOBs onto your top-level ports. Check your documentation for "FPGA Compiler" (not FPGA Compiler II) which is what Synopsys calls Design Compiler with the fpga switch on. Or ask your Synopsys office there in Bangalore. Without that automatic inference of IOBs, they won't be in the EDIF file. Xilinx will just see 'clk' as an undriven net, and optimize it away. Alternately, you could structurally instantiate the IBUF/BUFG combination you need in the top-level Verilog module, and connect it to the clk net. Using Design Compiler for FPGAs is not the best choice for speed and area. DC will certainly do a good job and give you good results when used correctly. But FPGAs have their own synthesis characteristics, which are very different from ASICs. For example, an FPGA design optimized for speed is usually close to optimal in area, which is certainly not the case for ASICs. FPGA Express and FPGA Compiler II have an FPGA-specific synthesis engine. I work for Synopsys myself, though not on the synthesis side. Today I'm writing you in an personal capacity, as a fellow FPGA enthusiast, not representing Synopsys. I use the Xilinx Student Edition 2.1i at home on my Spartan2, and FPGA Compiler II v3.5 at work on Virtex. Good luck and let us know how it works out. --Mike Bharath Kumar wrote: > > Hi Mr.Jan, > > Thank you very much for replying... > Now i am realising that I have some problem in the synthesis itself... > Let me explain what's happening in my design.. > > I have a modules A and B. The module B is instantiated in module A. > As you rightly said, the clock is an external signal. > > verilog code is as follows > > module A( clk, data,.........); > > input clk; > . > . > . > > B b1 (clk,abc,......); > > .... > .. > .. > endmodule > > module B (clk,abc......); > > input clk; > > always @(posedge clk) > begin > .... > ... > end > .... > > endmodule > > *** In brief, i am simply passing signal 'clk' from module A ( which is the > top module) to module B. > Since there is no " always @ (posedge clk) " in the module A, the > synthesis tool is not able > to infer I/o buffer or pad... Am I right?????? > > *** If I instantiate a buffer component of xilinx in the RTL... Then it > becomes Xilinx dependent. > According to my knowledge, RTL should be technology independent. > > *** How to circumvent this problem...???? > > *** I am using Synopsys Design Compiler 1999.10 for synthesis and ' EDIF ' > from this i am giving to > Xilinx design manager... > > Pls help me. > > thanks, > Bharath > Bangalore, INDIA > > ----- Original Message ----- > From: Jan Gray <> > To: <> > Sent: Friday, January 05, 2001 10:30 AM > Subject: RE: [fpga-cpu] Xilinx bitgen problem > > > It appears that you are using a net, clk, that has no driver. I assume > you > > hope to use an external clock signal. You must bring it into the device > > (and reflect that in your design). > > > > In schematics, you instantiate an IPAD and connect it to an IBUF, and > > connect that to a BUFGP/BUFGS/BUFG. For one example, open the XSOC > > schematics in the Foundation editor, and/or review > /xsoc/doc/schematics.pdf > > in the XSOC Project Kit (via www.fpgacpu.org/xsoc/). > > > > In HDL, you need to declare clk as an input and use it as a synchronous > > control signal (e.g. > > module foo(clk, ...) > > input clk; ... > > always @(posedge clk) ... > > endmodule > > ) > > and that should suffice for the synthesis tool to infer it as a clock > input > > and provide the BUFG on your behalf. > > > > I recommend working through Dave Vanden Bout's 'Practical Xilinx Designer > > Lab Book' exercises for a tutorial introduction to all these beginning > > Xilinx issues. > > > > Jan Gray, Gray Research LLC > > > > > > To Post a message, send it to: > > To Unsubscribe, send a blank message to: > > > > > > To Post a message, send it to: > To Unsubscribe, send a blank message to: |
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