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Discussion Groups | FPGA-CPU | Memory Management
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Memory Management - Rob Finch - Dec 19 22:50:00 2004
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What kind of memory management features do the NIOS / Microblaze offer ? What would be appropriate for SoC systems ? I've been working on a simple segmented system, plus a bitmap for execute / write able memory. But I'm thinking maybe I'm making things too complex. I think I've found a way to use segment registers without having to mess with near / far pointers. I use the upper four bits of an address as an index into an array of sixteen segment registers. The segment registers then supply the base address for that segment which is added to the remainder of the address to form the physical address. It's kind of like using a simple mapping table on the upper four bits of the address to provide an extended address range, but I'm using it to supply a segment base instead. I think it should work.... (code addresses don't go through the segment system in order to increase performance, just the data addresses). Robert |
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Re: Memory Management - James - Dec 21 10:50:00 2004
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Unfortunately, at this time, Nios II doesn't provide any memory management features. What are you trying to achieve? As for your scheme, it would create a critical path on the address generation if you really perform an addition between the base address and offset to compute the physical address. Instead, if you force the base address to be properly aligned, you can perfom a contatenation of the base address with the offset which would eliminate the critical path. It is conceivable that you could modify the Nios II source code to make this change. We don't actually write code directly in Verilog or VHDL. Instead, we have a set of perl libraries (called Europa) that generate the Verilog or VHDL when you generate in SOPC Builder. The files are in c:\altera\kits\altera_nios2\components\altera_nios2. +james+ --- In , "Rob Finch" <robfinch@s...> wrote: > > What kind of memory management features do the NIOS / Microblaze > offer ? What would be appropriate for SoC systems ? > > I've been working on a simple segmented system, plus a bitmap for > execute / write able memory. But I'm thinking maybe I'm making things > too complex. I think I've found a way to use segment registers > without having to mess with near / far pointers. I use the upper four > bits of an address as an index into an array of sixteen segment > registers. The segment registers then supply the base address for > that segment which is added to the remainder of the address to form > the physical address. It's kind of like using a simple mapping table > on the upper four bits of the address to provide an extended address > range, but I'm using it to supply a segment base instead. I think it > should work.... (code addresses don't go through the segment system > in order to increase performance, just the data addresses). > > Robert |
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Re: Memory Management - Rob Finch - Dec 24 3:09:00 2004
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--- In , "James" <jalobaba@y...> wrote: > > Unfortunately, at this time, Nios II doesn't provide any memory > management features. What are you trying to achieve? Dynamic program loading, relocation of data while preserving short addressing forms (saves code space). Memory protection. > As for your scheme, it would create a critical path on the > address generation if you really perform an addition between > the base address and offset to compute the physical address. > Instead, if you force the base address to be properly aligned, > you can perfom a contatenation of the base address with the offset > which would eliminate the critical path. Yes it does create a critical path, I handle this by pipelining the address computation meaning loads/stores take an extra cycle. This affects performance by about 8% max. I estimate. (It turns a 3 cycle load/store into a 4 cycle load/store). > It is conceivable that you could modify the Nios II source code > to make this change. We don't actually write code directly in > Verilog or VHDL. Instead, we have a set of perl libraries (called > Europa) that generate the Verilog or VHDL when you generate in SOPC > Builder. > The files are in c:\altera\kits\altera_nios2 \components\altera_nios2. I've been studying the Nios II reference manual. It looks like a really good design. I've scrapped the segment idea anyway (I'm saving it for my ugly duckling processor). I can achive much the same result using a global pointer register. Robert |
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Re: Re: Memory Management - Jan Gray - Dec 24 17:50:00 2004
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If you have a virtually indexed (addressed) cache, code or data, you may only have to perform virtual -> physical address translation and certain page protection checks on a cache miss. Assuming reasonable cache hit rates, this can substantially reduce the MMU page translation overhead. But watch out, virtually indexed caches have several gotchas that physically indexed ones don't. Jan Gray |
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