This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
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While I'm not new to logic design, I'm about to get my feet wet with FPGAs, and was looking for opinions on the SP3 starter kit they are offering at their web store for 99 bucks.. Any comments, good or bad appreciated... |
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I have this board and have been using it for a couple of months while I work on building a CPU specifically for Pascal. I have built a peripheral for it: 2 rows of 8 hex digits controlled with a Maxim MAX6954 using SPI. It works very well. Probably the cheapest education you can buy! --- In , "Tony" <tony@i...> wrote: > While I'm not new to logic design, I'm about to get my feet wet > with FPGAs, and was looking for opinions on the SP3 starter kit > they are offering at their web store for 99 bucks.. > Any comments, good or bad appreciated... |
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You can't really go wrong with the Spartan-III kit @ $99. I already have a couple of Altera FPGA dev boards, and am thinking about getting the SP3. -marc On 12/24/04 7:22 PM, "rtstofer" <> wrote: > > > I have this board and have been using it for a couple of months while > I work on building a CPU specifically for Pascal. I have built a > peripheral for it: 2 rows of 8 hex digits controlled with a Maxim > MAX6954 using SPI. It works very well. > > Probably the cheapest education you can buy! > > --- In , "Tony" <tony@i...> wrote: >> While I'm not new to logic design, I'm about to get my feet wet >> with FPGAs, and was looking for opinions on the SP3 starter kit >> they are offering at their web store for 99 bucks.. >> >> >> Any comments, good or bad appreciated... > To post a message, send it to: > To unsubscribe, send a blank message to: > Yahoo! Groups Links |
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Hi Tony, The Spartan 3 board is good value for money. It has 1MByte of Fast SRAM that can be up to 32 bits wide. It has VGA interface, although rather limitted with only 8 colours. It has PS/2 keyboard connector, RS232 port, 8 switches and 8 (?) push buttons, 4 x 7 segment display and 8 discrete LEDS. It also has built in configuartion Flash. It uses only a 200Kgate device, (dare I use K gates as a unit of capacity) and has a fixed clock of 50 MHz. Boards like Tony Burch's B5-X300 are larger and have a better array peripherals, such as compact Flash and IDE disk interfaces and a programamble clock, but the Spartan 3 starter board gets you going very ecconomically. I started of with Tony Burch's Spartan B3+, a number of years ago, then upgraded to a B5-X300 board so have a certain loyalty to those boards. The Spartan 3 starter board I purchased earlier this year and managed to port my 6809 clone onto it with a VDU although It was a very tight fit. The Spartan 3 has 2K x 8/9 bit Block RAMs which is nice and the logic blocks that can be used to implement 18 bit hardware multipliers make it better suited to high speed DSP applications, although I have not tried using them for that as yet. John. Tony wrote: >While I'm not new to logic design, I'm about to get my feet wet >with FPGAs, and was looking for opinions on the SP3 starter kit >they are offering at their web store for 99 bucks.. >Any comments, good or bad appreciated... -- http://members.optushome.com.au/jekent |
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Overall, the kit is good thing for its price. However, it lacks peripherals. Maybe Xess (www.xess.com) boards are also a nice option! Regards, JaaC --- Tony <> wrote: > While I'm not new to logic design, I'm about to get > my feet wet > with FPGAs, and was looking for opinions on the SP3 > starter kit > they are offering at their web store for 99 bucks.. > Any comments, good or bad appreciated... ===== Jaime Andrés Aranguren Cardona __________________________________ |
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Well, it does have some peripherals: serial I/O (with a lame attempt at a second port), VGA output and PS/2 input (all assuming, of course, that you implement the devices). Code is given but it revolves around microblaze. Nevertheless, many VHDL examples at www.opencores.com work with little effort. John Kent has a 6809 with VGA text and PS/2 input at http://members.optushome.com.au/jekent/system09/index.html. Look near the bottom of the page where the title specifies the Spartan 3 Starter Board. I started to look at adding a compact flash device for a disk drive but I haven't worked it out as yet. Should be easy enough. Same code would work for an IDE drive. I know it is doable because I have two CFs on the BurchED B5-300 as disk drives for CP/M running on the T80 core. --- In , Jaime Andres Aranguren Cardona <jaime_aranguren@y...> wrote: > Overall, the kit is good thing for its price. > However, it lacks peripherals. > > Maybe Xess (www.xess.com) boards are also a nice > option! > > Regards, > > JaaC > > --- Tony <tony@i...> wrote: > > > > > While I'm not new to logic design, I'm about to get > > my feet wet > > with FPGAs, and was looking for opinions on the SP3 > > starter kit > > they are offering at their web store for 99 bucks.. > > > > > > Any comments, good or bad appreciated... > > ===== > > Jaime Andrés Aranguren Cardona > jaime.aranguren@i... > jaime.aranguren@c... > > > __________________________________ |
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> looking for opinions on the SP3 starter kit > they are offering at their web store for 99 bucks. > > Any comments, good or bad appreciated... It's a great value. I'm thinking about buying more of them. When I was trying to get a PS/2 keyboard working with it, I initially overlooked the section of the documentation that describes the jumper for 5V vs. 3.3V power to the PS/2 port. So far, having the factory default be 3.3V is the only misfeature I've found, and that's easily corrected by moving the jumper. I wish they offered it with an XC3S400, but the XC3S200 is big enough to do quite a lot of interesting stuff. I'm considering laying out my own proto board for the XC3S1000 and XC3S1500, which are the largest parts officially supported by WebPack. Eric |
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Looks like the xess stuff might be better when i get the hang of things.. Doubt ill ever go and start designing boards for anything i do, it looks like thier stuff would be more suited to when im out of 'learning' mode. Looks like the xilinx oem edu-board was the right place to start. thanks all! > ________________________________________________________________________ > > Message: 1 > Date: Sat, 25 Dec 2004 09:57:41 -0800 (PST) > From: Jaime Andres Aranguren Cardona <> > Subject: Re: Spartan 3 Starter Kit? > > Overall, the kit is good thing for its price. > However, it lacks peripherals. > > Maybe Xess (www.xess.com) boards are also a nice > option! > > Regards, > > JaaC > > --- Tony <> wrote: > > > > > While I'm not new to logic design, I'm about to get > > my feet wet > > with FPGAs, and was looking for opinions on the SP3 > > starter kit > > they are offering at their web store for 99 bucks.. > > > > > > Any comments, good or bad appreciated... > > > ------------------------------------------------------------------------ |
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Why do they only put a single PS2 port on most boards ? You need TWO to connect both a keyboard and a mouse. |
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Rob Finch wrote: >Why do they only put a single PS2 port on most boards ? You need TWO >to connect both a keyboard and a mouse. > The altium live design boards have two but no config prom (unless you buy a config addon from Tony Birch). Same price as the S3 starter kit. Haven't tried using them direct from ise or quartus yet. For the starter kit make your own extra ps2 port on veroboard or get a DIO4 or 5 addon board or get a wirewrap or other board and make it on that Digilentinc are coming up with some nice addons hbridge boards, usb2 for io and config, ethernet , etc Alex -- No virus found in this outgoing message. Checked by AVG Anti-Virus. Version: 7.0.298 / Virus Database: 265.6.5 - Release Date: 26/12/2004 |
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The retrocomnputing baseboard from trenz electronic has two PS2 ports. http://www.trenz-electronic.de/prod/proden20.htm http://shop.trenz-electronic.de/catalog/default.php?cPath=1_27 It also has a legacy joystick port and is therefore ideally suited for arcade game projects. Kolja Sulimma Rob Finch wrote: >Why do they only put a single PS2 port on most boards ? You need TWO >to connect both a keyboard and a mouse. |
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Trenz has a very nice product line. However, I couldn't find a price for the retrocomputing baseboard. I wonder if it is actually available at this point. --- In , Kolja Sulimma <kolja@s...> wrote: > The retrocomnputing baseboard from trenz electronic has two PS2 ports. > > http://www.trenz-electronic.de/prod/proden20.htm > http://shop.trenz-electronic.de/catalog/default.php?cPath=1_27 > > It also has a legacy joystick port and is therefore ideally suited for > arcade game projects. > > Kolja Sulimma > > Rob Finch wrote: > > >Why do they only put a single PS2 port on most boards ? You need TWO > >to connect both a keyboard and a mouse. > > > |
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It is listed in the shop (the 2nd link below). The price is 149€ plus VAT. Also, the XC3S400 and XC3S1000 versions of the micromodule are sitting on my desk for testing and will be available any moment now. Kolja Sulimma rtstofer wrote: >Trenz has a very nice product line. However, I couldn't find a >price for the retrocomputing baseboard. > >I wonder if it is actually available at this point. > >--- In , Kolja Sulimma <kolja@s...> wrote: >>The retrocomnputing baseboard from trenz electronic has two PS2 >> >> >ports. >>http://www.trenz-electronic.de/prod/proden20.htm >>http://shop.trenz-electronic.de/catalog/default.php?cPath=1_27 >> >>It also has a legacy joystick port and is therefore ideally suited >> >> >for >>arcade game projects. >> >>Kolja Sulimma >> >> > |
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With the advent of the XC3S1000, it prompted me to wonder what I really wanted in an FPGA board. I'm getting tired of playing with 8 bit micro clones with PS2, VGA and RS232 interfaces. Been there ... done that. The XC3S1000 hopefully gives more scope to play with more serious hardware designs. Apart from the usual interfaces listed above, I thought the following features would be nice: 1. 32 Bit wide RAM The Spartan 3 Starter board has this. Static RAM is faster and easier to use, but DRAM is larger To run a 32 bit CPU design such as microblaze with uCLinux and the like, I think you need DRAM. DRAM is also nice to implement some serious graphics accelerators. 2. Ethernet Interface. A simple 10/100 Base T connector with isolation transformer can't be too hard to implement. 3. Compact Flash interface. Some boards have this already, but many do not. 4. Video Codec. It would be nice to have video in as well as video out. I'm told that cameras with digital interfaces are becoming more prevelant (I'm thinking of cheap mobile phone camera inserts rather than full blown commercial digital video cameras), although I have not been able to find any on the web. 5. PCI Bus slot. For softcore processors it would be nice to be able to use existing PC hardware. There are some basic PCI controllers around, alough it would be good to develop something a bit better. 6. Flash ROM for boot code. I'd prefer to keep Block RAM on the Xilinx free for things like cache memory, or MMUs etc. where speed is critical. Off course adding too much overhead hardware can make the board hopelessly expensive, so the trick is to keep the design simple. Add on modules are the key to keeping expensive options off the main board, but have their own associated costs with additional connectors etc. What do other people think ? John. -- http://members.optushome.com.au/jekent |
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John Kent wrote: >6. Flash ROM for boot code. >I'd prefer to keep Block RAM on the Xilinx free for >things like cache memory, or MMUs etc. where speed >is critical. You can use preinitialized caches with locked cache lines that contain code to copy data from NAND-Flash to SRAM. Once the boot code is finished the cache lines can be unlocked to increase the cache size. Lockable cache lines aren't a bad idea anyway for embedded applications because you can implement fixed latency interrupt handlers that way. Kolja Sulimma . |
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> The retrocomnputing baseboard from trenz electronic has two PS2 ports. > > http://www.trenz-electronic.de/prod/proden20.htm > http://shop.trenz-electronic.de/catalog/default.php?cPath=1_27 > > It also has a legacy joystick port and is therefore ideally suited for > arcade game projects. That's close to what I'm looking for. But I'm looking for something with 32 bit wide SRAM. A network interface would be nice too (CS8900 ?).The audio output needs to be buffered too so it can drive a pair of PC speakers. A jumper programmable PLL oscillator would be nice too, it makes it possible for someone else to match frequencies without having to hunt around for crystals. It would be nice to have an interface to one of the newer joysticks / game controllers. A C64 joystick might be hard to find. It would be nice to have 4096 colors available (4x4x4 bits RGB). It could quite easily be driven by a color lookup table in the FPGA (translate 8 to 12 bits). The most important thing I'm looking for right now is a larger FPGA supported by free software. I've maxed out my XC2S300e..... The 3S1500 looks interesting... Rob |
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> With the advent of the XC3S1000, it prompted me to wonder > what I really wanted in an FPGA board. > I'm getting tired of playing with 8 bit micro clones with PS2, VGA > and RS232 interfaces. Been there ... done that. > > The XC3S1000 hopefully gives more scope to play with more > serious hardware designs. I hear ya. I've had to pick and choose what to include in my SoC and go with simpler smaller hardware in order to get things to fit. > Apart from the usual interfaces listed above, > I thought the following features would be nice: > > 1. 32 Bit wide RAM > The Spartan 3 Starter board has this. > Static RAM is faster and easier to use, but DRAM is larger > To run a 32 bit CPU design such as microblaze with uCLinux > and the like, I think you need DRAM. DRAM is also nice > to implement some serious graphics accelerators. SDRAM is tricky to use. You need to use fifo's, cache's and burst ram access to get any performance out of it. I think I'd prefer 512k x 32b sram. 2MB is probably enough for a pared down version of linux. How about putting a couple of SDRAM module connectors on the board (only 32 bits would have to be connected up) then offering sram modules that could be plugged into the same connectors. Since the FPGA IOs are reprogrammable it could support either SDRAM or SRAM in the same module connector. Then it would be up to the user to decide what type of RAM they wanted, rather than it being a fixed feature of the board. > 2. Ethernet Interface. > A simple 10/100 Base T connector with isolation transformer > can't be too hard to implement. I'd like to see something like a CS8900. > 3. Compact Flash interface. > Some boards have this already, but many do not. > > 4. Video Codec. > It would be nice to have video in as well as video out. > I'm told that cameras with digital interfaces are becoming > more prevelant (I'm thinking of cheap mobile phone camera > inserts rather than full blown commercial digital video cameras), > although I have not been able to find any on the web. > > 5. PCI Bus slot. > For softcore processors it would be nice to be able > to use existing PC hardware. There are some basic PCI > controllers around, alough it would be good to develop > something a bit better. > I'm not sure about this one. PCI is tricky to interface to. Everything you might want a PCI slot for is also already on the motherboard. Most of the PCI slots in my PC sit empty. I'd prefer to see some sort of expansion header(s) with some standardized signals (address / data) to allow custom hardware development. > 6. Flash ROM for boot code. > I'd prefer to keep Block RAM on the Xilinx free for > things like cache memory, or MMUs etc. where speed > is critical. > Off course adding too much overhead hardware can make the > board hopelessly expensive, so the trick is to keep the design > simple. Add on modules are the key to keeping expensive options > off the main board, but have their own associated costs with > additional connectors etc. > > What do other people think ? A couple of other options I'd like to see are: 1) a battery backed up real time clock / calandar. A computer isn't a computer without a RTC. 2) an IDE hard drive connector or two. But please NO floppy connector. 3) buffered audio output to drive a pair of PC speakers. But please no complicated DAC/ADC chips. It's easy enough to build a delta-sigma DAC in the FPGA, and it uses fewer IOs as well. Rob |
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> You have 4 clock synthesizers in a Spartan-3. What else do you need from > a pll? Lower jitter than 100ps? No. I used the wrong term maybe. I'd just like an oscillator that can be programmed to operate at any frequency. I like the ICS525 ? on the BurchEd board. Suppose I want to generate a 57.272727MHz clock (that's 16x color burst so the frequency has to be fairly accurate), can it be done fairly easily without using all the DCMs ? > XC3S1000 is available from Trenz. Does it work with the retro-computing carrier ? Rob |
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Caution: I just did exactly that with my burch ed b5 board and the accuracy wasn't good enough to generate the color burst and chroma carrier without fractionally stepping through a SIN rom to correct for the clock inaccuracy. That can be done with any clock speed over 4x (2x?) the color burst clock. It was very very very difficult to track down the problem as my oscillator was only off by a few hz. Scott Williamson ----- Original Message ----- From: "Robert Finch" <> To: <> Sent: Tuesday, December 28, 2004 2:16 PM Subject: Re: [fpga-cpu] Re: Spartan 3 Starter Kit? > You have 4 clock synthesizers in a Spartan-3. What else do you need from > a pll? Lower jitter than 100ps? No. I used the wrong term maybe. I'd just like an oscillator that can be programmed to operate at any frequency. I like the ICS525 ? on the BurchEd board. Suppose I want to generate a 57.272727MHz clock (that's 16x color burst so the frequency has to be fairly accurate), can it be done fairly easily without using all the DCMs ? > XC3S1000 is available from Trenz. Does it work with the retro-computing carrier ? Rob To post a message, send it to: To unsubscribe, send a blank message to: Yahoo! Groups Links -- No virus found in this incoming message. Checked by AVG Anti-Virus. Version: 7.0.298 / Virus Database: 265.6.5 - Release Date: 12/26/2004 -- No virus found in this outgoing message. Checked by AVG Anti-Virus. Version: 7.0.298 / Virus Database: 265.6.5 - Release Date: 12/26/2004 |
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Hi Rob, Robert Finch wrote: >I hear ya. I've had to pick and choose what to include in my SoC and go with >simpler smaller hardware in order to get things to fit. > > >SDRAM is tricky to use. You need to use fifo's, cache's and burst ram access >to get any performance out of it. I think I'd prefer 512k x 32b sram. 2MB is >probably enough for a pared down version of linux. >How about putting a couple of SDRAM module connectors on the board (only 32 >bits would have to be connected up) then offering sram modules that could be >plugged into the same connectors. Since the FPGA IOs are reprogrammable it >could support either SDRAM or SRAM in the same module connector. Then it >would be up to the user to decide what type of RAM they wanted, rather than >it being a fixed feature of the board. > I was thinking of 3D video accelerators where you need a fair amount of RAM for the Z Buffer. >>2. Ethernet Interface. >>A simple 10/100 Base T connector with isolation transformer >>can't be too hard to implement. >> >> > >I'd like to see something like a CS8900. > The CS8900 is very popular for embedded designs. At CSIRO where I used to work, they decided to go with a Power QUICC (8560 ?) to provide all the micro peripherals for their FPGA board. The idea was they could be more cheaply implemented in dedicated silicon than on an FPGA, but it sort of defeats the purpose of experimenting with FPGAs. Looking around at combined processor and FPGA boards they work out fairly pricey. Most of the boards I have seen have had pretty small FPGAs on them. >I'm not sure about this one. PCI is tricky to interface to. Everything you >might want a PCI slot for is also already on the motherboard. Most of the >PCI slots in my PC sit empty. I'd prefer to see some sort of expansion >header(s) with some standardized signals (address / data) to allow custom >hardware development. > Yeah I guess. I was thinking that you did not want to put too much dedicated hardware on the board such at video encoders etc, because it made the board so expensive. By adding a PCI slot you could use a cheap video card or even a Bt848 based video capture card. Drivers are readily available for linux. Most of the low price FPGA board vendors probably don't want to standardise on a common bus. 1. Because they want to lock customers into their range of peripherals 2. They probably couldn't agree on a standard anyway :-) >A couple of other options I'd like to see are: >1) a battery backed up real time clock / calandar. A computer isn't a >computer without a RTC. >2) an IDE hard drive connector or two. But please NO floppy connector. >3) buffered audio output to drive a pair of PC speakers. But please no >complicated DAC/ADC chips. It's easy enough to build a delta-sigma DAC in >the FPGA, and it uses fewer IOs as well. > >Rob > There are a few things I'd like the ADC/DAC for. 1. Video, so I can play with some skeleton and clustering algorithms that have been in the back of my mind. 2. Audio, for sound processing 3. RF, for Direct Digital Synthesis. This has to be high resolution, accurate and fast. RF & Video, may require something a bit more sophistocated than an R-2R network on an I/O port or delta-sigma DAC. John. -- http://members.optushome.com.au/jekent [Non-text portions of this message have been removed] |
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Hi Kolja, Thats not a bad idea. It does mean that there needs to be a bulk storage device to boot from, but then you need that anyway. cool. John. Kolja Sulimma wrote: >You can use preinitialized caches with locked cache lines that contain >code to copy data from NAND-Flash to SRAM. >Once the boot code is finished the cache lines can be unlocked to >increase the cache size. >Lockable cache lines aren't a bad idea anyway for embedded applications >because you can implement fixed latency interrupt handlers that way. > >Kolja Sulimma >. -- http://members.optushome.com.au/jekent |
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I just want a large FPGA and the Flash with a JTAG interface and a maximum number of uncommited pins led to an edge connector of some type. MAYBE a bunch of SRAM configurable as 8/16/32 bit width. This on the main board to keep speed up. If the board uses a card-edge connector then I want to be able to buy a motherboard and peripherals that plug into the motherboard. Maybe the first peripheral board is the Swiss Army Knife: 2 serial, 1 parallel, VGA, 2 PS/2, 1 or 2 USB. Maybe ethernet. Then, at least a 3rd slot on the motherboard for prototyping. By the way, there should be an adequate number of ground signals to keep logic signals in line. The connectors on the Starter Board don't impress me much - when I built my 16 digit HEX display I used Connector B and now my development platform is nearly 12" long. There is probably a better way to use the connectors but it didn't occur to me at the time. Or, I'll just buy the Xess XSA-3S1000 when the new peripheral board becomes available. I can't say I'm enchanted with the DRAM but I can probably live with it - but only 16 bits wide? Maybe not... The Trenz stuff looks pretty good but the exchange rate makes it kind of pricey in US$. --- In , John Kent <jekent@o...> wrote: > Hi Kolja, > > Thats not a bad idea. It does mean that there needs to be a bulk storage > device to boot from, > but then you need that anyway. cool. > > John. > > Kolja Sulimma wrote: > > > > >You can use preinitialized caches with locked cache lines that contain > >code to copy data from NAND-Flash to SRAM. > >Once the boot code is finished the cache lines can be unlocked to > >increase the cache size. > >Lockable cache lines aren't a bad idea anyway for embedded applications > >because you can implement fixed latency interrupt handlers that way. > > > >Kolja Sulimma > >. > > > > > > -- > http://members.optushome.com.au/jekent |
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> type. MAYBE a bunch of SRAM configurable as 8/16/32 bit width. > This on the main board to keep speed up. With the 9/18/36 bit wide block ram, it's tempting to create an 18 bit wide processor. It'd be nice to have 9/18/36 bit wide external ram as well. Rob |
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rtstofer wrote: >The Trenz stuff looks pretty good but the exchange rate makes it >kind of pricey in US$. I talked to Thorsten Trenz about this and we decided to offer a huge discount for a Micromodule/Retrocomputing bundle: You can order the XC3S200 Micromodule and the Retrocomputing Baseboard together for 199€. This offer might take a few days to make it into the shop. http://www.trenz-electronic.de/prod/proden20.htm >I just want a large FPGA and the Flash with a JTAG interface and a >maximum number of uncommited pins led to an edge connector of some type. > We decided to use 0.8mm wieson SMD connectors to provide 120 user I/Os. The connectors are easy to solder by hand and the pitch is coarse enough to fit enough vias with standard board design rules. (0.4mm drill, 0.2mm spacing, 0.2mm restring) The micromodule is great as a basis for you own homebrew fpga board. All the difficult stuff is taken care off: bga soldering, multilayer board, four different power supply voltages, low impedance decoupling, configuration, etc. Now you can carry on building a low cost two layer board for you peripherals. >By the way, there should be an adequate number of ground signals to >keep logic signals in line. Keep in mind that power supply signals have the same effekt as gnd signals if there are decoupling caps close to the connector pins. There are 20 GND/Supply pins on each micromodule connector and most signals are routed as differential pairs. Enough advertisement, Kolja Sulimma |
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--- In , John Kent <jekent@o...> wrote: > Hi Rob, > > I was thinking of 3D video accelerators where you need a fair > amount of RAM for the Z Buffer. It would be nice to have two or more independant DDR ports for that > The CS8900 is very popular for embedded designs. And also well supported ... |
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Scott- > I just did exactly that with my burch ed b5 board and the accuracy > wasn't good enough to generate the color burst and chroma carrier > without fractionally stepping through a SIN rom to correct for the > clock inaccuracy. That can be done with any clock speed over 4x > (2x?) the color burst clock. It was very very very difficult to > track down the problem as my oscillator was only off by a few hz. You used the onboard chip (not FPGA) but it was not accurate enough? Have you tried using a DCM yet? Was it accurate enough? Thanks. I'm trying to be sure I understand your advice. -Jeff > ----- Original Message ----- > From: "Robert Finch" <> > To: <> > Sent: Tuesday, December 28, 2004 2:16 PM > Subject: Re: [fpga-cpu] Re: Spartan 3 Starter Kit? > > > You have 4 clock synthesizers in a Spartan-3. What else do you need from > > a pll? Lower jitter than 100ps? > > No. I used the wrong term maybe. I'd just like an oscillator that can be > programmed to operate at any frequency. I like the ICS525 ? on the BurchEd > board. Suppose I want to generate a 57.272727MHz clock (that's 16x color > burst so the frequency has to be fairly accurate), can it be done fairly > easily without using all the DCMs ? > > > XC3S1000 is available from Trenz. > > > > Does it work with the retro-computing carrier ? > > Rob |
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> Caution: > I just did exactly that with my burch ed b5 board and the accuracy wasn't > good enough to generate the color burst and chroma carrier > without fractionally stepping through a SIN rom to correct for the clock > inaccuracy. That can be done with any clock speed over 4x > (2x?) the color burst clock. It was very very very difficult to track > down the problem as my oscillator was only off by a few hz. > > Scott Williamson I've done a little bit of work on displaying stuff on the TV, but I haven't been satisfied with the results. The text is just too blurry when going through a composite input. However I was able to get a fairly accurate color burst and chroma carrier results. I cheated a bit and used a modification of the AppleII output circuitry, feeding the burst into a LC filter, and combining other signals (sync / video) using about half a dozen resistors and a transistor. Cleaning up the burst signal with an LC filter seemed to help a lot. I stepped through a 16 entry SIN/COS rom to do the color modulation at 16x the burst frequency. Without a proper modulator (needs to multiply) the pixel rate is limited to a multiple of the color burst frequency. The 16x modulation worked okay for an 8.18MHz pixel rate (I was emulating the C64 graphics). Operating at a higher frequency may help. I think the DLL's / PLL have trouble operating below 20 MHz when you need a really accurate clock What's the minimum DLL / PLL frequency ? Could the problem have been clock jitter ? I can't remember if I picked the most accurate clock frequency, or the lowest jitter. Rob |
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Jeff, The programmable clock is on the prototype board and not in the FPGA. It could not hit the color burst frequency exactly, it only hit 57272720 hz as opposed to 57272727.27 hz. Once I detected the problem, I was able to fix it and move on. In short I used fractional fixed point math: The SIN ROM only has 16 values and I planned on just walking through the table to generate values on every clock. I ended up increasing the index from 4 bits to 20 bits and only using the upper 4 bits as the index. The remaining lower bits become a fractional accumulator. The following line adds 1.000274658203125 to the index each clock. 1 + x"0012"/x"10000" dsinidx <= dsinidx + (x"10012"); Scott ----- Original Message ----- From: "Jeff Brower" <> To: <> Sent: Thursday, December 30, 2004 3:39 PM Subject: Re: [fpga-cpu] Re: Spartan 3 Starter Kit? Scott- > I just did exactly that with my burch ed b5 board and the accuracy > wasn't good enough to generate the color burst and chroma carrier > without fractionally stepping through a SIN rom to correct for the > clock inaccuracy. That can be done with any clock speed over 4x > (2x?) the color burst clock. It was very very very difficult to > track down the problem as my oscillator was only off by a few hz. You used the onboard chip (not FPGA) but it was not accurate enough? Have you tried using a DCM yet? Was it accurate enough? Thanks. I'm trying to be sure I understand your advice. -Jeff > ----- Original Message ----- > From: "Robert Finch" <> > To: <> > Sent: Tuesday, December 28, 2004 2:16 PM > Subject: Re: [fpga-cpu] Re: Spartan 3 Starter Kit? > > > You have 4 clock synthesizers in a Spartan-3. What else do you need from > > a pll? Lower jitter than 100ps? > > No. I used the wrong term maybe. I'd just like an oscillator that can be > programmed to operate at any frequency. I like the ICS525 ? on the BurchEd > board. Suppose I want to generate a 57.272727MHz clock (that's 16x color > burst so the frequency has to be fairly accurate), can it be done fairly > easily without using all the DCMs ? > > > XC3S1000 is available from Trenz. > > > > Does it work with the retro-computing carrier ? > > Rob To post a message, send it to: To unsubscribe, send a blank message to: Yahoo! Groups Links -- No virus found in this incoming message. Checked by AVG Anti-Virus. Version: 7.0.298 / Virus Database: 265.6.6 - Release Date: 12/28/2004 -- No virus found in this outgoing message. Checked by AVG Anti-Virus. Version: 7.0.298 / Virus Database: 265.6.7 - Release Date: 12/30/2004 |
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The frequency of 16 x the chroma carrier 57.27272727 MHZ is extremly stable, just not right on the mark, my clock generator generates 57272720 Hz, easily accounted for once detected. I reiterate that I'm getting beautiful results with just 16 resistors as output, and I could probably do without a couple of the lower bits and not notice. My display as a novelty is modeled after the Atari 800 display, the simplest thing I know very well, I used to work for Atari. It's 320x192 pixels with a significant dead band border for TV. Each pixel is 1/2 a color clock wide and I turned off interlacing. I have a 320x240 5 bit RGB bitmap layer that comes from the de-bayered output of a 640x480 imager and a text overlay layer, VERY useful in debugging. I grabbed the font from an old Atari 800 ROM image. I also use an Atari Joystick for input but I am not working on an emulator or anything. The resolution is fine for what I'm doing and I could easily go up to 640x480 though the image would extend off the screen vertically and there would be aliasing against the color clock in high contrast areas, but then again I have that now at 320 resolution. Scott Williamson ----- Original Message ----- From: "Robert Finch" <> To: <> Sent: Friday, December 31, 2004 5:27 AM Subject: Re: [fpga-cpu] Re: Spartan 3 Starter Kit? > Caution: > I just did exactly that with my burch ed b5 board and the accuracy wasn't > good enough to generate the color burst and chroma carrier > without fractionally stepping through a SIN rom to correct for the clock > inaccuracy. That can be done with any clock speed over 4x > (2x?) the color burst clock. It was very very very difficult to track > down the problem as my oscillator was only off by a few hz. > > Scott Williamson I've done a little bit of work on displaying stuff on the TV, but I haven't been satisfied with the results. The text is just too blurry when going through a composite input. However I was able to get a fairly accurate color burst and chroma carrier results. I cheated a bit and used a modification of the AppleII output circuitry, feeding the burst into a LC filter, and combining other signals (sync / video) using about half a dozen resistors and a transistor. Cleaning up the burst signal with an LC filter seemed to help a lot. I stepped through a 16 entry SIN/COS rom to do the color modulation at 16x the burst frequency. Without a proper modulator (needs to multiply) the pixel rate is limited to a multiple of the color burst frequency. The 16x modulation worked okay for an 8.18MHz pixel rate (I was emulating the C64 graphics). Operating at a higher frequency may help. I think the DLL's / PLL have trouble operating below 20 MHz when you need a really accurate clock What's the minimum DLL / PLL frequency ? Could the problem have been clock jitter ? I can't remember if I picked the most accurate clock frequency, or the lowest jitter. Rob To post a message, send it to: To unsubscribe, send a blank message to: Yahoo! Groups Links -- No virus found in this incoming message. Checked by AVG Anti-Virus. Version: 7.0.298 / Virus Database: 265.6.7 - Release Date: 12/30/2004 -- No virus found in this outgoing message. Checked by AVG Anti-Virus. Version: 7.0.298 / Virus Database: 265.6.7 - Release Date: 12/30/2004 |
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The nuhorizons board ? http://www.nuhorizons.com/sp3/ Not available yet, they also have other addon cards for adc/dac if you need faster than the on board ones. Digilent are also supposedly working on a S3-1000 gate version board. Their usb module is very good, still haven't got around to trying the ethernet module. List of spartan3 boards http://www.xilinx.com/xlnx/xebiz/search/searchresult.jsp?_ResultsView=Board&_ProgramType=&ProgramType=XilinxOnBoard&searchJSP=%2Fxebiz%2Fsearch%2Fboardsrch.jsp&sGlobalNavPick=&sSecondaryNavPick=&_IPProducts=Development+Board&_IPCategory=&_IPSubcategory=&_DeviceSupport_1127=Spartan-3&_Vendor=&_SearchText=&resultNumber=50&Submit+Search.x=45&Submit+Search.y=7 Expensive For the suzaku board (used for microblaze course at UQ) http://www.hitechglobal.com/boards/suzaku.htm tokyo electron http://www.hitechglobal.com/boards/allboards.htm More expensive than the trenz board and no webpack support xilinx ml-401 http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&key=HW-V4-ML401-USA picture http://www.xilinx.com/bvdocs/images/ipcenter/product_images/HW-V4_ML401_l.jpg Another lower cost board is altera's cubic cyclonium http://www.altera.com/education/demonstrations/tools/cubic-cyclonium/onl-cubic-cyclonium.html http://www.shopaltera.com/category.asp?catalog%5Fname=ALC&category%5Fname=Demo+Tools&Page=1 US$149 Cyclone (1C6), 168 ledmatrix display, sdram video dac FMS3818(3x 8bit - 8 bit per color) ,EPCS4 config (4Mb) 8MB (32 bit ) sdram programmed via usb blaster(built-in) , powered via usb problem is very limited user io - 10 pins only provide 1 example design(few slightly different versions of it) based on nios (NIOS 1) Alex rtstofer wrote: >I just want a large FPGA and the Flash with a JTAG interface and a >maximum number of uncommited pins led to an edge connector of some >type. MAYBE a bunch of SRAM configurable as 8/16/32 bit width. >This on the main board to keep speed up. > >If the board uses a card-edge connector then I want to be able to >buy a motherboard and peripherals that plug into the motherboard. >Maybe the first peripheral board is the Swiss Army Knife: 2 serial, >1 parallel, VGA, 2 PS/2, 1 or 2 USB. Maybe ethernet. > >Then, at least a 3rd slot on the motherboard for prototyping. > >By the way, there should be an adequate number of ground signals to >keep logic signals in line. > >The connectors on the Starter Board don't impress me much - when I >built my 16 digit HEX display I used Connector B and now my >development platform is nearly 12" long. There is probably a better >way to use the connectors but it didn't occur to me at the time. > >Or, I'll just buy the Xess XSA-3S1000 when the new peripheral board >becomes available. I can't say I'm enchanted with the DRAM but I >can probably live with it - but only 16 bits wide? Maybe not... > >The Trenz stuff looks pretty good but the exchange rate makes it >kind of pricey in US$. > >--- In , John Kent <jekent@o...> wrote: >>Hi Kolja, >> >>Thats not a bad idea. It does mean that there needs to be a bulk >> >> >storage >>device to boot from, >>but then you need that anyway. cool. >> >>John. >> >>Kolja Sulimma wrote: >> >> >> >>>You can use preinitialized caches with locked cache lines that >>> >>> >contain >>>code to copy data from NAND-Flash to SRAM. >>>Once the boot code is finished the cache lines can be unlocked to >>>increase the cache size. >>>Lockable cache lines aren't a bad idea anyway for embedded >>> >>> >applications >>>because you can implement fixed latency interrupt handlers that >>> >>> >way. >>>Kolja Sulimma >>>. >>> >>> >>> >>> >>-- >>http://members.optushome.com.au/jekent >> > -- No virus found in this outgoing message. Checked by AVG Anti-Virus. Version: 7.0.298 / Virus Database: 265.6.7 - Release Date: 30/12/2004 |
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Scott- > The programmable clock is on the prototype board and not in the FPGA. It could not hit the color burst frequency exactly, it only > hit 57272720 hz as opposed to 57272727.27 hz. Thanks... that's what I thought, just wanted to be sure. > Once I detected the problem, I was able to fix it and move on. > > In short I used fractional fixed point math: The SIN ROM only has 16 values and I planned on just walking through the table to > generate values on every clock. I ended up increasing the index from 4 bits to 20 bits and only using the upper 4 bits as the > index. The remaining lower bits become a fractional accumulator. > > The following line adds 1.000274658203125 to the index each clock. 1 + x"0012"/x"10000" > > dsinidx <= dsinidx + (x"10012"); Ok so the osc input is "processed" with the Sin lookup table, and the final output is an FPGA pin. What about using DCM, for example 10 MHz input with 63/11 multiplier? Would the ppm be good enough> -Jeff > ----- Original Message ----- > From: "Jeff Brower" <> > To: <> > Sent: Thursday, December 30, 2004 3:39 PM > Subject: Re: [fpga-cpu] Re: Spartan 3 Starter Kit? > > Scott- > > > I just did exactly that with my burch ed b5 board and the accuracy > > wasn't good enough to generate the color burst and chroma carrier > > without fractionally stepping through a SIN rom to correct for the > > clock inaccuracy. That can be done with any clock speed over 4x > > (2x?) the color burst clock. It was very very very difficult to > > track down the problem as my oscillator was only off by a few hz. > > You used the onboard chip (not FPGA) but it was not accurate enough? > > Have you tried using a DCM yet? Was it accurate enough? > > Thanks. I'm trying to be sure I understand your advice. > > -Jeff > > > ----- Original Message ----- > > From: "Robert Finch" <> > > To: <> > > Sent: Tuesday, December 28, 2004 2:16 PM > > Subject: Re: [fpga-cpu] Re: Spartan 3 Starter Kit? > > > > > You have 4 clock synthesizers in a Spartan-3. What else do you need from > > > a pll? Lower jitter than 100ps? > > > > No. I used the wrong term maybe. I'd just like an oscillator that can be > > programmed to operate at any frequency. I like the ICS525 ? on the BurchEd > > board. Suppose I want to generate a 57.272727MHz clock (that's 16x color > > burst so the frequency has to be fairly accurate), can it be done fairly > > easily without using all the DCMs ? > > > > > XC3S1000 is available from Trenz. > > > > > > > Does it work with the retro-computing carrier ? > > > > Rob |
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Jeff, Does anyone know why my posts are taking days to reach the group? re:"Ok so the osc input is "processed" with the Sin lookup table, and the final output is an FPGA pin." I had intended to integer step through the 16 value table once each clock tick but it required the timing finessing described below. Technically for an NTSC composite chroma output the chroma subcarrier needs to be superimposed on the luminance signal where the chroma signals amplitude represents color saturation and phase relative to the chroma burst represents the hue. My "processing" actually does a RGB to YIQ matrix operation using SIN & COS values for the wave. The final output is 8 digital 3.3V output pins connected to 16 resistors in an R-2R ladder D to A configuration to generate the needed analog output, but I believe you get the idea. What is a DCM? If the 10MHZ was accurate, 64/11 would certainly generate the needed 5.727272727MHZ clock. I have heard of using clock frequencies as low as 4x the color burst frequency and applying a 7Mhz low pass filter to the output. I believe you can still get decent color output because the phase & amplitude of the chroma signal could be represented adequately by the amplitude of the 4 samples of 3.79mhz wave though I have not done anything except what I have described below. I certainly wouldn't use less, in the best case you would output 1, 0, -1, 0... in the worst case at 45 degrees you would output .7, .7, -.7, -.7... Scott ----- Original Message ----- From: "Jeff Brower" <> To: <> Sent: Sunday, January 02, 2005 6:49 PM Subject: Re: [fpga-cpu] Re: Spartan 3 Starter Kit? Scott- > The programmable clock is on the prototype board and not in the FPGA. It could not hit the color burst frequency exactly, it only > hit 57272720 hz as opposed to 57272727.27 hz. Thanks... that's what I thought, just wanted to be sure. > Once I detected the problem, I was able to fix it and move on. > > In short I used fractional fixed point math: The SIN ROM only has 16 values and I planned on just walking through the table to > generate values on every clock. I ended up increasing the index from 4 bits to 20 bits and only using the upper 4 bits as the > index. The remaining lower bits become a fractional accumulator. > > The following line adds 1.000274658203125 to the index each clock. 1 + x"0012"/x"10000" > > dsinidx <= dsinidx + (x"10012"); Ok so the osc input is "processed" with the Sin lookup table, and the final output is an FPGA pin. What about using DCM, for example 10 MHz input with 63/11 multiplier? Would the ppm be good enough> -Jeff > ----- Original Message ----- > From: "Jeff Brower" <> > To: <> > Sent: Thursday, December 30, 2004 3:39 PM > Subject: Re: [fpga-cpu] Re: Spartan 3 Starter Kit? > > Scott- > > > I just did exactly that with my burch ed b5 board and the accuracy > > wasn't good enough to generate the color burst and chroma carrier > > without fractionally stepping through a SIN rom to correct for the > > clock inaccuracy. That can be done with any clock speed over 4x > > (2x?) the color burst clock. It was very very very difficult to > > track down the problem as my oscillator was only off by a few hz. > > You used the onboard chip (not FPGA) but it was not accurate enough? > > Have you tried using a DCM yet? Was it accurate enough? > > Thanks. I'm trying to be sure I understand your advice. > > -Jeff > > > ----- Original Message ----- > > From: "Robert Finch" <> > > To: <> > > Sent: Tuesday, December 28, 2004 2:16 PM > > Subject: Re: [fpga-cpu] Re: Spartan 3 Starter Kit? > > > > > You have 4 clock synthesizers in a Spartan-3. What else do you need from > > > a pll? Lower jitter than 100ps? > > > > No. I used the wrong term maybe. I'd just like an oscillator that can be > > programmed to operate at any frequency. I like the ICS525 ? on the BurchEd > > board. Suppose I want to generate a 57.272727MHz clock (that's 16x color > > burst so the frequency has to be fairly accurate), can it be done fairly > > easily without using all the DCMs ? > > > > > XC3S1000 is available from Trenz. > > > > > > > Does it work with the retro-computing carrier ? > > > > Rob To post a message, send it to: To unsubscribe, send a blank message to: Yahoo! Groups Links -- No virus found in this incoming message. Checked by AVG Anti-Virus. Version: 7.0.298 / Virus Database: 265.6.7 - Release Date: 12/30/2004 -- No virus found in this outgoing message. Checked by AVG Anti-Virus. Version: 7.0.298 / Virus Database: 265.6.7 - Release Date: 12/30/2004 |
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> Does anyone know why my posts are taking days to reach the group? To preclude most spam to this list, it became necessary for new members' posts to be moderated (requiring explicit approval) until I promote each such new (demonstrated non-spammer) member to unmoderated status. Sometimes that takes a few days, or worse -- sometimes I overlook it and eventually one of our unsung but esteemed assistant moderators steps in and approves the message backlog. I'll try to do better in 2005. (Happy new year, everyone.) I'm thinking of writing a script to promote everyone who has been a member for a certain period of time (30 days or so) to unmoderated status by default. Stay tuned. Jan Gray, list moderator |
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Scott- > Does anyone know why my posts are taking days to reach the group? > > re:"Ok so the osc input is "processed" with the Sin lookup table, and the final output is > an FPGA pin." > > I had intended to integer step through the 16 value table once each clock tick but it required the timing finessing described below. > Technically for an NTSC composite chroma output the chroma subcarrier needs to be superimposed on the luminance signal where the > chroma signals amplitude represents color saturation and phase relative to the chroma burst represents the hue. My "processing" > actually does a RGB to YIQ matrix operation using SIN & COS values for the wave. > > The final output is 8 digital 3.3V output pins connected to 16 resistors in an R-2R ladder D to A configuration to generate the > needed analog output, but I believe you get the idea. > > What is a DCM? If the 10MHZ was accurate, 64/11 would certainly generate the needed 5.727272727MHZ clock. My understanding (and I'm sure on this group I will get corrected fast if wrong) is that Spartan 3 has 4x DCMs, and they have a multiply/divide feature that allows a range of clock generation. I'm curious to learn if a DCM-generated video clock would have sufficient ppm. I'm working on a dual-channel (2 full independent channel) video enc/dec DSP module, and I keep dreaming about removing some of the oscillators and possibly even the Philips encoders on the board. That could save a lot of space. -Jeff > I have heard of using clock frequencies as low as 4x the color burst frequency and applying a 7Mhz low pass filter to the output. I > believe you can still get decent color output because the phase & amplitude of the chroma signal could be represented adequately by > the amplitude of the 4 samples of 3.79mhz wave though I have not done anything except what I have described below. I certainly > wouldn't use less, in the best case you would output 1, 0, -1, 0... in the worst case at 45 degrees you would output .7, > .7, -.7, -.7... > > Scott > > ----- Original Message ----- > From: "Jeff Brower" <> > To: <> > Sent: Sunday, January 02, 2005 6:49 PM > Subject: Re: [fpga-cpu] Re: Spartan 3 Starter Kit? > > Scott- > > > The programmable clock is on the prototype board and not in the FPGA. It could not hit the color burst frequency exactly, it only > > hit 57272720 hz as opposed to 57272727.27 hz. > > Thanks... that's what I thought, just wanted to be sure. > > > Once I detected the problem, I was able to fix it and move on. > > > > In short I used fractional fixed point math: The SIN ROM only has 16 values and I planned on just walking through the table to > > generate values on every clock. I ended up increasing the index from 4 bits to 20 bits and only using the upper 4 bits as the > > index. The remaining lower bits become a fractional accumulator. > > > > The following line adds 1.000274658203125 to the index each clock. 1 + x"0012"/x"10000" > > > > dsinidx <= dsinidx + (x"10012"); > > Ok so the osc input is "processed" with the Sin lookup table, and the final output is > an FPGA pin. > > What about using DCM, for example 10 MHz input with 63/11 multiplier? Would the ppm > be good enough> > > -Jeff > > > ----- Original Message ----- > > From: "Jeff Brower" <> > > To: <> > > Sent: Thursday, December 30, 2004 3:39 PM > > Subject: Re: [fpga-cpu] Re: Spartan 3 Starter Kit? > > > > Scott- > > > > > I just did exactly that with my burch ed b5 board and the accuracy > > > wasn't good enough to generate the color burst and chroma carrier > > > without fractionally stepping through a SIN rom to correct for the > > > clock inaccuracy. That can be done with any clock speed over 4x > > > (2x?) the color burst clock. It was very very very difficult to > > > track down the problem as my oscillator was only off by a few hz. > > > > You used the onboard chip (not FPGA) but it was not accurate enough? > > > > Have you tried using a DCM yet? Was it accurate enough? > > > > Thanks. I'm trying to be sure I understand your advice. > > > > -Jeff > > > > > ----- Original Message ----- > > > From: "Robert Finch" <> > > > To: <> > > > Sent: Tuesday, December 28, 2004 2:16 PM > > > Subject: Re: [fpga-cpu] Re: Spartan 3 Starter Kit? > > > > > > > You have 4 clock synthesizers in a Spartan-3. What else do you need from > > > > a pll? Lower jitter than 100ps? > > > > > > No. I used the wrong term maybe. I'd just like an oscillator that can be > > > programmed to operate at any frequency. I like the ICS525 ? on the BurchEd > > > board. Suppose I want to generate a 57.272727MHz clock (that's 16x color > > > burst so the frequency has to be fairly accurate), can it be done fairly > > > easily without using all the DCMs ? > > > > > > > XC3S1000 is available from Trenz. > > > > > > > > > > Does it work with the retro-computing carrier ? > > > > > > Rob > > To post a message, send it to: > To unsubscribe, send a blank message to: > Yahoo! Groups Links > > -- > No virus found in this incoming message. > Checked by AVG Anti-Virus. > Version: 7.0.298 / Virus Database: 265.6.7 - Release Date: 12/30/2004 > > -- > No virus found in this outgoing message. > Checked by AVG Anti-Virus. > Version: 7.0.298 / Virus Database: 265.6.7 - Release Date: 12/30/2004 > > To post a message, send it to: > To unsubscribe, send a blank message to: > Yahoo! Groups Links |
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Scott- > Does anyone know why my posts are taking days to reach the group? > > re:"Ok so the osc input is "processed" with the Sin lookup table, and the final output is > an FPGA pin." > > I had intended to integer step through the 16 value table once each clock tick but it required the timing finessing described below. > Technically for an NTSC composite chroma output the chroma subcarrier needs to be superimposed on the luminance signal where the > chroma signals amplitude represents color saturation and phase relative to the chroma burst represents the hue. My "processing" > actually does a RGB to YIQ matrix operation using SIN & COS values for the wave. > > The final output is 8 digital 3.3V output pins connected to 16 resistors in an R-2R ladder D to A configuration to generate the > needed analog output, but I believe you get the idea. > > What is a DCM? If the 10MHZ was accurate, 64/11 would certainly generate the needed 5.727272727MHZ clock. My understanding (and I'm sure on this group I will get corrected fast if wrong) is that Spartan 3 has 4x DCMs, and they have a multiply/divide feature that allows a range of clock generation. I'm curious to learn if a DCM-generated video clock would have sufficient ppm. I'm working on a dual-channel (2 full independent channel) video enc/dec DSP module, and I keep dreaming about removing some of the oscillators and possibly even the Philips encoders on the board. That could save a lot of space. -Jeff > I have heard of using clock frequencies as low as 4x the color burst frequency and applying a 7Mhz low pass filter to the output. I > believe you can still get decent color output because the phase & amplitude of the chroma signal could be represented adequately by > the amplitude of the 4 samples of 3.79mhz wave though I have not done anything except what I have described below. I certainly > wouldn't use less, in the best case you would output 1, 0, -1, 0... in the worst case at 45 degrees you would output .7, > .7, -.7, -.7... > > Scott > > ----- Original Message ----- > From: "Jeff Brower" <> > To: <> > Sent: Sunday, January 02, 2005 6:49 PM > Subject: Re: [fpga-cpu] Re: Spartan 3 Starter Kit? > > Scott- > > > The programmable clock is on the prototype board and not in the FPGA. It could not hit the color burst frequency exactly, it only > > hit 57272720 hz as opposed to 57272727.27 hz. > > Thanks... that's what I thought, just wanted to be sure. > > > Once I detected the problem, I was able to fix it and move on. > > > > In short I used fractional fixed point math: The SIN ROM only has 16 values and I planned on just walking through the table to > > generate values on every clock. I ended up increasing the index from 4 bits to 20 bits and only using the upper 4 bits as the > > index. The remaining lower bits become a fractional accumulator. > > > > The following line adds 1.000274658203125 to the index each clock. 1 + x"0012"/x"10000" > > > > dsinidx <= dsinidx + (x"10012"); > > Ok so the osc input is "processed" with the Sin lookup table, and the final output is > an FPGA pin. > > What about using DCM, for example 10 MHz input with 63/11 multiplier? Would the ppm > be good enough> > > -Jeff > > > ----- Original Message ----- > > From: "Jeff Brower" <> > > To: <> > > Sent: Thursday, December 30, 2004 3:39 PM > > Subject: Re: [fpga-cpu] Re: Spartan 3 Starter Kit? > > > > Scott- > > > > > I just did exactly that with my burch ed b5 board and the accuracy > > > wasn't good enough to generate the color burst and chroma carrier > > > without fractionally stepping through a SIN rom to correct for the > > > clock inaccuracy. That can be done with any clock speed over 4x > > > (2x?) the color burst clock. It was very very very difficult to > > > track down the problem as my oscillator was only off by a few hz. > > > > You used the onboard chip (not FPGA) but it was not accurate enough? > > > > Have you tried using a DCM yet? Was it accurate enough? > > > > Thanks. I'm trying to be sure I understand your advice. > > > > -Jeff > > > > > ----- Original Message ----- > > > From: "Robert Finch" <> > > > To: <> > > > Sent: Tuesday, December 28, 2004 2:16 PM > > > Subject: Re: [fpga-cpu] Re: Spartan 3 Starter Kit? > > > > > > > You have 4 clock synthesizers in a Spartan-3. What else do you need from > > > > a pll? Lower jitter than 100ps? > > > > > > No. I used the wrong term maybe. I'd just like an oscillator that can be > > > programmed to operate at any frequency. I like the ICS525 ? on the BurchEd > > > board. Suppose I want to generate a 57.272727MHz clock (that's 16x color > > > burst so the frequency has to be fairly accurate), can it be done fairly > > > easily without using all the DCMs ? > > > > > > > XC3S1000 is available from Trenz. > > > > > > > > > > Does it work with the retro-computing carrier ? > > > > > > Rob > > To post a message, send it to: > To unsubscribe, send a blank message to: > Yahoo! Groups Links > > -- > No virus found in this incoming message. > Checked by AVG Anti-Virus. > Version: 7.0.298 / Virus Database: 265.6.7 - Release Date: 12/30/2004 > > -- > No virus found in this outgoing message. > Checked by AVG Anti-Virus. > Version: 7.0.298 / Virus Database: 265.6.7 - Release Date: 12/30/2004 > > To post a message, send it to: > To unsubscribe, send a blank message to: > Yahoo! Groups Links |
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Kolja- > >My understanding (and I'm sure on this group I will get corrected fast if wrong) is > >that Spartan 3 has 4x DCMs, and they have a multiply/divide feature that allows a > >range of clock generation. > > > >I'm curious to learn if a DCM-generated video clock would have sufficient ppm. > > > The frequency of the DCM output will be exactly the input frequeny > multiplied by N/M with N and M beeing an integer in the range of 1 to > 31. That's 0pppm. > The worst case jitter is 100ps, which is not particulary good, but on > the other hand the ICS525 which you are comparing against specifies a > jitter of 145ps. > > Something different: > Instead of a fractional accumulator to step through your sine table you > could use bresenhams algorithm. It will give you a higher accuracy with > less bits. Thanks Kolja that helps me a lot -- so the ppm will be whatever the input osc rate is *N/M. -Jeff |
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Eric- > I mentioned in another posting that the official spec is > 3,579,545 +/- 10 Hz. That's a tolerance of +/- 2.79 PPM, so > basically any crystal source is going to require tweaking to meet > that spec. AFAIK, you can't buy crystals with good enough specs > other than as an expensive crystal ovens. > > Most devices that attempt to produce NTSC to broadcast spec either > have a trimmer on the crystal osciallator, or derive their timing > from an externally supplied 5 or 10 MHz frequency reference, which > is usually a rubidium or cesium oscillator, or a GPS-stabilized > crystal oven. > > However, TVs and monitors will generally accept a wider range than > +/- 10 Hz, so cheap consumer electronics often just uses an > untrimmed crystal and is not expected to actually be within the > standard tolerance. > > If you are using a programmable oscillator (e.g., a crystal oscillator > with a PLL or DLL), you have to worry about both the PPM spec of the > reference oscillator and any error or jitter introduced by the PLL > or DLL. Thanks, this is very helpful. We have to support a range of resolutions up to D1. Based on your info it appears we should stick with the VCO approach, which is what we have in our board design currently, and not rely on DCMs. Although we can experiment with the DCMs for video clocks when we have the chance. -Jeff |