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Discussion Groups | FPGA-CPU | Re: loop counters

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

loop counters - Rob Finch - Dec 24 3:21:00 2004


One thing that I'd like to see in a cpu is a loop counter. A loop
counter doesn't take hardly any hardware resources, and it can really
offer a performance benefit in some circumstances. For example, if a
256k graphics screen is being cleared, being able to clear the screen
10-20% faster would be great. Interruptable string instructions would
be nice too.

Rob




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Re: loop counters - erikc - Dec 24 12:14:00 2004


----- Original Message -----
From: "Rob Finch" <>
To: <>
Sent: Friday, December 24, 2004 08:21
Subject: [fpga-cpu] loop counters >
>
> One thing that I'd like to see in a cpu is a loop counter.
A loop
> counter doesn't take hardly any hardware resources, and it
can really
> offer a performance benefit in some circumstances. For
example, if a
> 256k graphics screen is being cleared, being able to clear
the screen
> 10-20% faster would be great. Interruptable string
instructions would
> be nice too.
>
> Rob

Here is what I would do: I would have a pair of registers,
one would be a hardware down-counter and the other would be
simply a pointer. Then, I'd create two instructions: The
first one I call "REPEAT" which would load the hardware
down-counter with a value and at the same time, fill the
pointer register with the address of the instruction after
the REPEAT. The other instruction would be "LOOP", which
would be essentially a conditional jump to the address held
in the pointer if the counter is nonzero and to the
instruction immediately following LOOP if the counter is
zero. If I wanted to go overboard, I could make these
registers the top of a two- or three- level stack so I could
do nested loops. In this case, REPEAT would do a push
before loading the registers and LOOP would do a pop when
the loop is finished.

Regarding strings, has anybody ever actually built a CPU
specifically intended and optimised for string-type
operations?

erikc





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Re: loop counters - Author Unknown - Dec 24 19:37:00 2004


--- In , "Rob Finch" <robfinch@s...> wrote:
>
> One thing that I'd like to see in a cpu is a loop counter. A loop
> counter doesn't take hardly any hardware resources, and it can
really
> offer a performance benefit in some circumstances. For example, if
a
> 256k graphics screen is being cleared, being able to clear the
screen
> 10-20% faster would be great. Interruptable string instructions
would
> be nice too.

Yes, I saw that in the Forth chip designed by Chuck Moore, they have
registers to support loop control. But don't most CPUs have
instructions to use a register as a counter for whatever, including
loop control? I added this capability to my return stack, but it is
not one instruction. One instruction adjusts a count on the top of
return stack setting flags. This can be used to check for zero or
carry for a down counter. A JMPZ or JMPC will cycle around on the
loop. Or you can use a second instruction with an up count to compare
the top of return stack to the second on return stack to test for end
of loop. Again a JMPZ or JMPC will cycle the loop.

Isn't that doable on most CPUs though?





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Re: loop counters - Eric Smith - Dec 25 20:13:00 2004

Rob wrote:
> One thing that I'd like to see in a cpu is a loop counter. A loop
> counter doesn't take hardly any hardware resources,

Present in many DSP chips, e.g. Motorola 5600x, 563xx. There's no
particular reason why you couldn't design one into a general-purpose
processor.

Of course, if you only have one, a compiler can probably only use
it in leaf functions. But that's the only place you actually
need it.

Eric




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Re: loop counters - Rob Finch - Dec 27 3:48:00 2004


> Present in many DSP chips, e.g. Motorola 5600x, 563xx. There's no
> particular reason why you couldn't design one into a general-purpose
> processor.
>
> Of course, if you only have one, a compiler can probably only use
> it in leaf functions. But that's the only place you actually
> need it. It's those leaf functions like strcpy or memmove that can get called
zillions of times that can really affect performance.

Okay, so I added a loop counter to my cpu. Then I went nuts and added
a repeat instruction, allowing any following instruction to be
repeated (including calls!)

Now I'm thinking of adding a block repeat instruction, allowing up to
16 following instructions to be repeated as a block. I'd have to
cache the instructions, but I see an easy way to do it.

I've got Tiny BASIC running on my SoC !!!

Rob



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Re: loop counters - Robert Finch - Dec 31 8:59:00 2004

> Regarding strings, has anybody ever actually built a CPU
> specifically intended and optimised for string-type
> operations? When I read this, the first thing that came to mind was a processor with 256
byte wide registers, 256 byte wide barrel shifter, parallel character search
instructions, etc....
That could be an interesting cpu design. But I suspect it would be slow. How
about using an entire block ram as a register ? And incorporating operations
like LEFT(), RIGHT(), MID() as basic processor instructions ? Of course,
saving and restoring those 256 byte registers during an interrupt might
impact interrupt latency. Rob




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Re: loop counters - Jeff Brower - Dec 31 14:42:00 2004

Robert-

> When I read this, the first thing that came to mind was a processor with 256
> byte wide registers, 256 byte wide barrel shifter, parallel character search
> instructions, etc....
> That could be an interesting cpu design. But I suspect it would be slow. How
> about using an entire block ram as a register ? And incorporating operations
> like LEFT(), RIGHT(), MID() as basic processor instructions ? Of course,
> saving and restoring those 256 byte registers during an interrupt might
> impact interrupt latency.

What about "shadow" registers? When an interrupt occurs, 256 registers are
transferred to their shadows -- no stack or other operations required. I've seen
this on ADI DSPs before.

-Jeff





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Re: loop counters - Robert Finch - Dec 31 18:16:00 2004

> What about "shadow" registers? When an interrupt occurs, 256 registers
> are
> transferred to their shadows -- no stack or other operations required.
> I've seen
> this on ADI DSPs before. I suppose there could be two register sets, one for interrupts and one for
normal operations. The block rams are only 16 bits wide max, so it would
still take time to transfer between registers. Having a set of string
registers in addition to regular integer registers might work out okay. It
could be handled like floating point registers are in some systems, where
the register set isn't actually saved off unless the program needs to use
the registers. I'm thinking that many strings are short, and if the string
length was tracked you'd only need to save / restore up to the length of the
string. We have integer registers, and floating point registers. The next
step seems to be string registers. It's the next data type.

How about a processor that can execute BASIC code directly ?

I've been thinking about this a little bit as I'm in the process of adding
string handling to Tiny BASIC.

Rob






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Re: loop counters - woodelf - Jan 1 12:03:00 2005

Robert Finch wrote:

>How about a processor that can execute BASIC code directly I think some of the HP computers years
ago did that in micro code.

>I've been thinking about this a little bit as I'm in the process of adding
>string handling to Tiny BASIC. Well then it is not so tiny.
Only in BASIC is strings 255 characters,
I think 1 byte is used for length.

>Rob PS. I like plain text messages, not HTML.




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